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src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode 

Pointer to opcode increases by unit uint16_t not byte.

Change-Id: I2986ca5402ad86d80e0eb955478bfbdc5d50e1f5
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/29339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
This commit is contained in:
Philipp Hug 2018-10-29 17:55:55 +01:00 committed by Ronald G. Minnich
parent bb7f41d85a
commit d4ab5bbc82
1 changed files with 1 additions and 1 deletions
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src/arch/riscv/misaligned.c
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@ -160,7 +160,7 @@ static int fetch_16bit_instruction(uintptr_t vaddr, uintptr_t *insn, int *size)
static int fetch_32bit_instruction(uintptr_t vaddr, uintptr_t *insn, int *size)
{
uint32_t l = (uint32_t)mprv_read_mxr_u16((uint16_t *)vaddr + 0);
uint32_t h = (uint32_t)mprv_read_mxr_u16((uint16_t *)vaddr + 2);
uint32_t h = (uint32_t)mprv_read_mxr_u16((uint16_t *)vaddr + 1);
uint32_t ins = (h << 16) | l;
if ((EXTRACT_FIELD(ins, 0x3) == 3) &&
(EXTRACT_FIELD(ins, 0x1c) != 0x7)) {