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sb/intel/lynxpoint: Enable PCIe Clock PM and ASPM L1 

Enable PCIe Clock power management and ASPM L1 substate by default. This
matches what Broadwell does.

Change-Id: Ic2bbcbc23d6bab0900d3e90ad8e2fbfa4aea3c16
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2021-10-12 21:01:13 +02:00 committed by Nico Huber
parent 5412a81485
commit d4ba2b14ca
1 changed files with 6 additions and 0 deletions
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6
src/southbridge/intel/lynxpoint/Kconfig
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@ -68,6 +68,12 @@ config PCIEXP_AER
bool bool
default y default y
config PCIEXP_CLK_PM
default y
config PCIEXP_L1_SUB_STATE
default y
config SERIALIO_UART_CONSOLE config SERIALIO_UART_CONSOLE
bool "Use SerialIO UART for console" bool "Use SerialIO UART for console"
depends on INTEL_LYNXPOINT_LP depends on INTEL_LYNXPOINT_LP