trival. All the changes is about comment and spaces.
1. Delete trailing white spaces. 2. Change the // comment to /* */. 3. Add some copyright header. 4. reindent. 5. delete multi blank lines. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Zheng Bao
Zheng Bao
parent
3c970eee2a
commit
d4c5c44d27
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@ -19,15 +19,15 @@
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#if CONFIG_RAMBASE >= 0x100000
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/* This is a lot more paranoid now, since Linux can NOT handle
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* being told there is a CPU when none exists. So any errors
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* will return 0, meaning no CPU.
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* being told there is a CPU when none exists. So any errors
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* will return 0, meaning no CPU.
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*
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* We actually handling that case by noting which cpus startup
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* and not telling anyone about the ones that dont.
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*/
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*/
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static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
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{
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return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000
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return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000
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}
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#endif
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@ -39,34 +39,34 @@ int lowmem_backup_size;
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extern char _secondary_start[];
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static void copy_secondary_start_to_1m_below(void)
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static void copy_secondary_start_to_1m_below(void)
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{
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#if CONFIG_RAMBASE >= 0x100000
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extern char _secondary_start_end[];
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unsigned long code_size;
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unsigned long start_eip;
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extern char _secondary_start_end[];
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unsigned long code_size;
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unsigned long start_eip;
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/* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S
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Also We need to copy the _secondary_start to the below 1M region
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*/
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start_eip = get_valid_start_eip((unsigned long)_secondary_start);
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code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
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/* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S
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Also We need to copy the _secondary_start to the below 1M region
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*/
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start_eip = get_valid_start_eip((unsigned long)_secondary_start);
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code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
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#if CONFIG_HAVE_ACPI_RESUME == 1
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/* need to save it for RAM resume */
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lowmem_backup_size = code_size;
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lowmem_backup = malloc(code_size);
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lowmem_backup_ptr = (char *)start_eip;
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if (lowmem_backup == NULL)
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die("Out of backup memory\n");
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memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size);
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memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size);
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#endif
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/* copy the _secondary_start to the ram below 1M*/
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memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
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/* copy the _secondary_start to the ram below 1M*/
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memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
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printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
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printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
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#endif
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}
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@ -75,7 +75,7 @@ static int lapic_start_cpu(unsigned long apicid)
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int timeout;
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unsigned long send_status, accept_status, start_eip;
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int j, num_starts, maxlvt;
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/*
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* Starting actual IPI sequence...
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*/
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@ -90,7 +90,7 @@ static int lapic_start_cpu(unsigned long apicid)
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/*
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* Send IPI
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*/
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lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT
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| LAPIC_DM_INIT);
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@ -104,7 +104,7 @@ static int lapic_start_cpu(unsigned long apicid)
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if (timeout >= 1000) {
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printk_err("CPU %ld: First apic write timed out. Disabling\n",
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apicid);
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// too bad.
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// too bad.
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printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
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if (lapic_read(LAPIC_ESR)) {
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printk_err("Try to reset ESR\n");
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@ -122,7 +122,7 @@ static int lapic_start_cpu(unsigned long apicid)
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/* Send IPI */
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lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
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printk_spew("Waiting for send to finish...\n");
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timeout = 0;
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do {
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@ -133,7 +133,7 @@ static int lapic_start_cpu(unsigned long apicid)
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if (timeout >= 1000) {
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printk_err("CPU %ld: Second apic write timed out. Disabling\n",
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apicid);
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// too bad.
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// too bad.
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return 0;
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}
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@ -244,10 +244,10 @@ int start_cpu(device_t cpu)
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/* Get an index for the new processor */
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index = ++last_cpu_index;
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/* Find end of the new processors stack */
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#if (CONFIG_RAMTOP>0x100000) && (CONFIG_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
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if(index<1) { // only keep bsp on low
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if(index<1) { // only keep bsp on low
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stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
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} else {
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// for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
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@ -265,7 +265,7 @@ int start_cpu(device_t cpu)
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stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
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#endif
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/* Record the index and which cpu structure we are using */
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info = (struct cpu_info *)stack_end;
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info->index = index;
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@ -339,7 +339,7 @@ void stop_this_cpu(void)
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printk_spew("Deasserting INIT.\n");
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/* Deassert the LAPIC INIT */
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lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
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lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
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lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
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printk_spew("Waiting for send to finish...\n");
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@ -391,7 +391,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
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}
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#if CONFIG_SERIAL_CPU_INIT == 0
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if(cpu==bsp_cpu) {
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continue;
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continue;
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}
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#endif
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@ -437,7 +437,7 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
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continue;
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}
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if (!cpu->initialized) {
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printk_err("CPU 0x%02x did not initialize!\n",
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printk_err("CPU 0x%02x did not initialize!\n",
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cpu->path.apic.apic_id);
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}
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}
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@ -480,22 +480,22 @@ void initialize_cpus(struct bus *cpu_bus)
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smm_init();
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#endif
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cpus_ready_for_init();
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cpus_ready_for_init();
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#if CONFIG_SMP == 1
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#if CONFIG_SERIAL_CPU_INIT == 0
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/* start all aps at first, so we can init ECC all together */
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start_other_cpus(cpu_bus, info->cpu);
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start_other_cpus(cpu_bus, info->cpu);
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#endif
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#endif
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/* Initialize the bootstrap processor */
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cpu_initialize();
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/* Initialize the bootstrap processor */
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cpu_initialize();
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#if CONFIG_SMP == 1
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#if CONFIG_SERIAL_CPU_INIT == 1
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start_other_cpus(cpu_bus, info->cpu);
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#endif
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#if CONFIG_SERIAL_CPU_INIT == 1
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start_other_cpus(cpu_bus, info->cpu);
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#endif
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/* Now wait the rest of the cpus stop*/
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wait_other_cpus_stop(cpu_bus);
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