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nb/intel/x4x: Fix computing page_size 

This variable needs to be in byte so a division by 8 needs to happen.

This problem was introduced by 3cf94032b "nb/x4x/raminit: Rewrite SPD
decode and timing selection", but was probably not encountered because
such dimms are rather uncommon.

Change-Id: I2d57f5e584ac7fa1479791c239432005fe8c178d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22991
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2017-12-25 17:01:33 +01:00 committed by Felix Held
parent 5a33d12c24
commit d4e5762bd7
1 changed files with 3 additions and 2 deletions
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5
src/northbridge/intel/x4x/raminit.c
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@ -183,9 +183,10 @@ static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
* 1KB page size. For the x16 configuration, the page size is 2KB
* for all densities except the 256Mb device, which has a 1KB page
* size." Micron, 'TN-47-16 Designing for High-Density DDR2 Memory'
* The formula is pagesize in KiB = width * 2^col_bits / 8.
*/
s->dimms[dimm_idx].page_size = s->dimms[dimm_idx].width *
(1 << decoded_dimm.col_bits);
s->dimms[dimm_idx].page_size = decoded_dimm.width *
(1 << decoded_dimm.col_bits) / 8;
switch (decoded_dimm.banks) {
case 4: