soc/intel/quark: Call FSP SiliconInit

Optionally relocate FSP into DRAM and then call FSP SiliconInit.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
   *  Add "select DISPLAY_FSP_ENTRY_POINTS"
   *  Add "select DISPLAY_HOBS"
   *  Optionally add "select RELOCATE_FSP_INTO_DRAM"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing is successful if:
   *  FSP entry points are displayed and
   *  The message "FspSiliconInit returned 0x00000000" is displayed and
   *  The HOBs are displayed correctly and
   *  The message "ERROR - Missing one or more required FSP HOBs!" is
not displayed

Change-Id: I91e660ea373a8bb00fc97fe8b760347cbfa96b1e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13631
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/soc/intel/quark/Kconfig

@@ -174,6 +174,13 @@ config FSP_ESRAM_LOC
 	help
 	  The location in ESRAM where a copy of the FSP binary is placed.
 
+config RELOCATE_FSP_INTO_DRAM
+	bool "Relocate FSP into DRAM"
+	default n
+	depends on PLATFORM_USES_FSP1_1
+	help
+	  Relocate the FSP binary into DRAM before the call to SiliconInit.
+
 #####
 # FSP PDAT binary
 #     The following options control the FSP platform data binary

src/soc/intel/quark/Makefile.inc

@@ -22,10 +22,12 @@ romstage-y += memmap.c
 romstage-y += tsc_freq.c
 romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
 
+ramstage-y += chip.c
 ramstage-y += memmap.c
 ramstage-y += tsc_freq.c
 ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
 
+CPPFLAGS_common += -I$(src)/soc/intel/quark
 CPPFLAGS_common += -I$(src)/soc/intel/quark/include
 
 # Chipset microcode path

src/soc/intel/quark/chip.c

@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "chip.h"
+#include <console/console.h>
+#include <fsp/ramstage.h>
+
+static void soc_init(void *chip_info)
+{
+	/* Perform silicon specific init. */
+	if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
+		intel_silicon_init();
+	else
+		fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0);
+}
+
+struct chip_operations soc_intel_quark_ops = {
+	CHIP_NAME("Intel Quark")
+	.init		= &soc_init,
+};

src/soc/intel/quark/chip.h

@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_CHIP_H_
+#define _SOC_CHIP_H_
+
+#include <stdint.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+
+struct soc_intel_quark_config {
+	uint32_t junk;
+};
+
+extern struct chip_operations soc_ops;
+
+#endif