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northbridge/intel/fsp_rangeley: Add space around operators 

Change-Id: Ia60729db83333c1159862cf604de321e3af8dcb1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16631
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2016-09-17 20:48:29 +02:00 committed by Patrick Georgi
parent a3d15afc67
commit d4fea5c675
3 changed files with 2 additions and 3 deletions
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2
src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
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@ -170,7 +170,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
void ChipsetFspReturnPoint(EFI_STATUS Status, void ChipsetFspReturnPoint(EFI_STATUS Status,
VOID *HobListPtr) VOID *HobListPtr)
{ {
*(void **)CBMEM_FSP_HOB_PTR=HobListPtr; *(void **)CBMEM_FSP_HOB_PTR = HobListPtr;
if (Status == 0xFFFFFFFF) { if (Status == 0xFFFFFFFF) {
soft_reset(); soft_reset();

1
src/northbridge/intel/fsp_rangeley/northbridge.c
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@ -86,7 +86,6 @@ static int add_fixed_resources(struct device *dev, int index)
struct resource *resource; struct resource *resource;
u32 pcie_config_base, pcie_config_size; u32 pcie_config_base, pcie_config_size;
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
"size=0x%x\n", pcie_config_base, pcie_config_size); "size=0x%x\n", pcie_config_base, pcie_config_size);

2
src/northbridge/intel/fsp_rangeley/udelay.c
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@ -19,7 +19,7 @@
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
/** /**
* Intel Rangeley CPUs always run the TSC at BCLK=100MHz * Intel Rangeley CPUs always run the TSC at BCLK = 100MHz
*/ */
/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. /* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow.