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soc/intel/cannonlake: Remove DMA support for PTT 

Alternative buffer communication support for PTT is no longer
needed for CNL onwards and coreboot does not need to reserve additional
4KiB memory for PTT support.

Change-Id: I11993cef77fd5e879eedabc1ed344f91f8257c90
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/27176
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2018-06-21 11:52:21 +05:30
parent f699c14c03
commit d5018a8f78
2 changed files with 0 additions and 23 deletions
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4
src/soc/intel/cannonlake/include/soc/iomap.h
View File

@ -65,10 +65,6 @@
#define HECI1_BASE_ADDRESS 0xfeda2000
/* PTT registers */
#define PTT_TXT_BASE_ADDRESS 0xfed30800
#define PTT_PRESENT 0x00070000
#define VTD_BASE_ADDRESS 0xFED90000
#define VTD_BASE_SIZE 0x00004000
/*

19
src/soc/intel/cannonlake/memmap.c
View File

@ -83,22 +83,6 @@ int smm_subregion(int sub, void **start, size_t *size)
return 0;
}
static bool is_ptt_enable(void)
{
if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) ==
PTT_PRESENT)
return true;
return false;
}
/* Calculate PTT size */
static size_t get_ptt_size(void)
{
/* Allocate 4KB for PTT if enabled */
return is_ptt_enable() ? 4*KiB : 0;
}
/* Calculate ME Stolen size */
static size_t get_imr_size(void)
{
@ -192,9 +176,6 @@ static size_t calculate_reserved_mem_size(uintptr_t dram_base,
/* Get Tracehub size */
reserve_mem_base -= get_imr_size();
/* Get PTT size */
reserve_mem_base -= get_ptt_size();
/* Traditional Area Size */
reserve_mem_size = dram_base - reserve_mem_base;