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{cpu,drivers}/amd: Replace MTRR addresses with macros 

Change-Id: I315c0b70c552c5dd7f640b18b913350bb88be81b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29173
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2018-10-17 20:18:17 +02:00 committed by Patrick Georgi
parent 253cd5a7e6
commit d50cf23e43
14 changed files with 50 additions and 50 deletions
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4
src/cpu/amd/agesa/family12/fixme.c
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@ -98,7 +98,7 @@ void amd_initmmio(void)
/* Set ROM cache onto WP to decrease post time */ /* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
} }

4
src/cpu/amd/agesa/family14/fixme.c
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@ -90,9 +90,9 @@ void amd_initmmio(void)
/* Set ROM cache onto WP to decrease post time */ /* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT; MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID; MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
/* Set P-state 0 (1600 MHz) early to save a few ms of boot time */ /* Set P-state 0 (1600 MHz) early to save a few ms of boot time */
MsrReg = 0; MsrReg = 0;

8
src/cpu/amd/agesa/family14/model_14_init.c
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@ -55,11 +55,11 @@ static void model_14_init(struct device *dev)
/* Set shadow WB, RdMEM, WrMEM */ /* Set shadow WB, RdMEM, WrMEM */
msr.lo = msr.hi = 0; msr.lo = msr.hi = 0;
wrmsr (0x259, msr); wrmsr(MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e; msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(0x250, msr); wrmsr(MTRR_FIX_64K_00000, msr);
wrmsr(0x258, msr); wrmsr(MTRR_FIX_16K_80000, msr);
for (msrno = 0x268; msrno <= 0x26f; msrno++) for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
wrmsr(msrno, msr); wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR); msr = rdmsr(SYSCFG_MSR);

4
src/cpu/amd/agesa/family15tn/fixme.c
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@ -76,7 +76,7 @@ void amd_initmmio(void)
/* Set ROM cache onto WP to decrease post time */ /* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
} }

10
src/cpu/amd/agesa/family15tn/model_15_init.c
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@ -54,12 +54,12 @@ static void model_15_init(struct device *dev)
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
msr.lo = msr.hi = 0; msr.lo = msr.hi = 0;
wrmsr (0x259, msr); wrmsr(MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e; msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(0x250, msr); wrmsr(MTRR_FIX_64K_00000, msr);
wrmsr(0x258, msr); wrmsr(MTRR_FIX_16K_80000, msr);
for (msrno = 0x268; msrno <= 0x26f; msrno++) for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
wrmsr (msrno, msr); wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR); msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;

4
src/cpu/amd/agesa/family16kb/fixme.c
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@ -76,7 +76,7 @@ void amd_initmmio(void)
/* Set ROM cache onto WP to decrease post time */ /* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
} }

10
src/cpu/amd/agesa/family16kb/model_16_init.c
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@ -52,12 +52,12 @@ static void model_16_init(struct device *dev)
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
msr.lo = msr.hi = 0; msr.lo = msr.hi = 0;
wrmsr (0x259, msr); wrmsr(MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e; msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(0x250, msr); wrmsr(MTRR_FIX_64K_00000, msr);
wrmsr(0x258, msr); wrmsr(MTRR_FIX_16K_80000, msr);
for (msrno = 0x268; msrno <= 0x26f; msrno++) for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
wrmsr (msrno, msr); wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR); msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;

4
src/cpu/amd/pi/00630F01/fixme.c
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@ -83,9 +83,9 @@ void amd_initmmio(void)
/* Set ROM cache onto WP to decrease post time */ /* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){ if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);

8
src/cpu/amd/pi/00630F01/model_15_init.c
View File

@ -54,11 +54,11 @@ static void model_15_init(struct device *dev)
* same as OntarioApMtrrSettingsList for APs * same as OntarioApMtrrSettingsList for APs
*/ */
msr.lo = msr.hi = 0; msr.lo = msr.hi = 0;
wrmsr(0x259, msr); wrmsr(MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e; msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(0x250, msr); wrmsr(MTRR_FIX_64K_00000, msr);
wrmsr(0x258, msr); wrmsr(MTRR_FIX_16K_80000, msr);
for (msrno = 0x268; msrno <= 0x26f; msrno++) for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
wrmsr(msrno, msr); wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR); msr = rdmsr(SYSCFG_MSR);

4
src/cpu/amd/pi/00660F01/fixme.c
View File

@ -89,9 +89,9 @@ void amd_initmmio(void)
/* Set ROM cache onto WP to decrease post time */ /* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) { if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);

8
src/cpu/amd/pi/00660F01/model_15_init.c
View File

@ -66,11 +66,11 @@ static void model_15_init(struct device *dev)
// BSP: make a0000-bffff UC, c0000-fffff WB // BSP: make a0000-bffff UC, c0000-fffff WB
msr.lo = msr.hi = 0; msr.lo = msr.hi = 0;
wrmsr(0x259, msr); wrmsr(MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e; msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(0x250, msr); wrmsr(MTRR_FIX_64K_00000, msr);
wrmsr(0x258, msr); wrmsr(MTRR_FIX_16K_80000, msr);
for (msrno = 0x268; msrno <= 0x26f; msrno++) for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
wrmsr(msrno, msr); wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR); msr = rdmsr(SYSCFG_MSR);

4
src/cpu/amd/pi/00730F01/fixme.c
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@ -94,9 +94,9 @@ void amd_initmmio(void)
/* Set ROM cache onto WP to decrease post time */ /* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) { if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);

8
src/cpu/amd/pi/00730F01/model_16_init.c
View File

@ -51,11 +51,11 @@ static void model_16_init(struct device *dev)
* same as OntarioApMtrrSettingsList for APs * same as OntarioApMtrrSettingsList for APs
*/ */
msr.lo = msr.hi = 0; msr.lo = msr.hi = 0;
wrmsr(0x259, msr); wrmsr(MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e; msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(0x250, msr); wrmsr(MTRR_FIX_64K_00000, msr);
wrmsr(0x258, msr); wrmsr(MTRR_FIX_16K_80000, msr);
for (msrno = 0x268; msrno <= 0x26f; msrno++) for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
wrmsr(msrno, msr); wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR); msr = rdmsr(SYSCFG_MSR);

20
src/drivers/amd/agesa/s3_mtrr.c
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@ -42,11 +42,11 @@ void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size)
wrmsr(SYSCFG_MSR, msr_data); wrmsr(SYSCFG_MSR, msr_data);
/* Fixed MTRRs */ /* Fixed MTRRs */
write_mtrr(&nvram_pos, 0x250); write_mtrr(&nvram_pos, MTRR_FIX_64K_00000);
write_mtrr(&nvram_pos, 0x258); write_mtrr(&nvram_pos, MTRR_FIX_16K_80000);
write_mtrr(&nvram_pos, 0x259); write_mtrr(&nvram_pos, MTRR_FIX_16K_A0000);
for (i = 0x268; i < 0x270; i++) for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_F8000; i++)
write_mtrr(&nvram_pos, i); write_mtrr(&nvram_pos, i);
/* Disable access to AMD RdDram and WrDram extension bits */ /* Disable access to AMD RdDram and WrDram extension bits */
@ -55,7 +55,7 @@ void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size)
wrmsr(SYSCFG_MSR, msr_data); wrmsr(SYSCFG_MSR, msr_data);
/* Variable MTRRs */ /* Variable MTRRs */
for (i = 0x200; i < 0x210; i++) for (i = MTRR_PHYS_BASE(0); i < MTRR_PHYS_BASE(8); i++)
write_mtrr(&nvram_pos, i); write_mtrr(&nvram_pos, i);
/* SYSCFG_MSR */ /* SYSCFG_MSR */
@ -89,21 +89,21 @@ void restore_mtrr(void)
msrPtr ++; msrPtr ++;
msr_data.hi = *msrPtr; msr_data.hi = *msrPtr;
msrPtr ++; msrPtr ++;
wrmsr(0x250, msr_data); wrmsr(MTRR_FIX_64K_00000, msr_data);
msr_data.lo = *msrPtr; msr_data.lo = *msrPtr;
msrPtr ++; msrPtr ++;
msr_data.hi = *msrPtr; msr_data.hi = *msrPtr;
msrPtr ++; msrPtr ++;
wrmsr(0x258, msr_data); wrmsr(MTRR_FIX_16K_80000, msr_data);
msr_data.lo = *msrPtr; msr_data.lo = *msrPtr;
msrPtr ++; msrPtr ++;
msr_data.hi = *msrPtr; msr_data.hi = *msrPtr;
msrPtr ++; msrPtr ++;
wrmsr(0x259, msr_data); wrmsr(MTRR_FIX_16K_A0000, msr_data);
for (msr = 0x268; msr <= 0x26F; msr++) { for (msr = MTRR_FIX_4K_C0000; msr <= MTRR_FIX_4K_F8000; msr++) {
msr_data.lo = *msrPtr; msr_data.lo = *msrPtr;
msrPtr ++; msrPtr ++;
msr_data.hi = *msrPtr; msr_data.hi = *msrPtr;
@ -117,7 +117,7 @@ void restore_mtrr(void)
wrmsr(SYSCFG_MSR, msr_data); wrmsr(SYSCFG_MSR, msr_data);
/* Restore the Variable MTRRs */ /* Restore the Variable MTRRs */
for (msr = 0x200; msr <= 0x20F; msr++) { for (msr = MTRR_PHYS_BASE(0); msr <= MTRR_PHYS_MASK(7); msr++) {
msr_data.lo = *msrPtr; msr_data.lo = *msrPtr;
msrPtr ++; msrPtr ++;
msr_data.hi = *msrPtr; msr_data.hi = *msrPtr;