Revert "mb/intel/shadowmountain: Add the ASL code"
This reverts commit 2151f7561d
.
Reason for revert: It depends on the shadowmountain ramstage patch.
Error on the builder:
IASL /cb-build/coreboot.0/default/INTEL_SHADOWMOUNTAIN/dsdt.aml
src/mainboard/intel/shadowmountain/dsdt.asl:4:10: fatal error: baseboard/ec.h: No such file or directory
#include <baseboard/ec.h>
^~~~~~~~~~~~~~~~
compilation terminated.
Change-Id: I9fa5e8cc2ad485bf82bfbda151bc46d26faef7ab
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
parent
2151f7561d
commit
d510b60f5b
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@ -1,8 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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#include <baseboard/ec.h>
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#include <baseboard/gpio.h>
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DefinitionBlock(
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"dsdt.aml",
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@ -14,31 +12,4 @@ DefinitionBlock(
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)
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{
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#include <acpi/dsdt_top.asl>
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#include <soc/intel/common/block/acpi/acpi/platform.asl>
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/* global NVS and variables */
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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/* CPU */
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#include <cpu/intel/common/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/alderlake/acpi/southbridge.asl>
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#include <soc/intel/alderlake/acpi/tcss.asl>
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}
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}
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/* Chrome OS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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// ACPI code for EC SuperIO functions
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#include <ec/google/chromeec/acpi/superio.asl>
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// ACPI code for EC functions
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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