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nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware 

8M was set in the assumption that at least 4M was needed for IED
(Intel Enhanced Debug) , but this is not true.

The SMRR MTRR's need to have TSEG aligned to its size which is easier when TSEG
is only 2M. Also at most 6M of RAM more becomes available for use.

Change-Id: I4b114c8dc13699b3c034f0a7060181d9d590737b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27873
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2018-08-06 15:50:54 +02:00 committed by Patrick Georgi
parent cf2941aec2
commit d522db048b
4 changed files with 16 additions and 10 deletions
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7
src/northbridge/intel/gm45/raminit.c
View File

@ -1242,12 +1242,13 @@ static void program_memory_map(const dimminfo_t *const dimms, const channel_mode
uma_sizem = (gms_sizek + gsm_sizek) >> 10;
}
/* TSEG 8M */
/* TSEG 2M, This amount can easily be covered by SMRR MTRR's,
which requires to have TSEG_BASE aligned to TSEG_SIZE. */
u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
reg8 &= ~0x7;
reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */
reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */
pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8);
uma_sizem += 8;
uma_sizem += 2;
}
const unsigned int mmio_size = get_mmio_size();

5
src/northbridge/intel/i945/early_init.c
View File

@ -191,10 +191,11 @@ static void i945_setup_bars(void)
if (gfxsize > 6)
gfxsize = 2;
pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4));
/* TSEG 2M, This amount can easily be covered by SMRR MTRR's,
which requires to have TSEG_BASE aligned to TSEG_SIZE. */
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
reg8 &= ~0x7;
reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */
reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */
pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8);
/* Set C0000-FFFFF to access RAM on both reads and writes */

6
src/northbridge/intel/pineview/raminit.c
View File

@ -2034,7 +2034,9 @@ static void sdram_mmap_regs(struct sysinfo *s)
gttsize = ggc_to_gtt[(ggc & 0x300) >> 8];
tom = s->channel_capacity[0];
tsegsize = 0x8; // 8MB
/* TSEG 2M, This amount can easily be covered by SMRR MTRR's,
which requires to have TSEG_BASE aligned to TSEG_SIZE. */
tsegsize = 0x2;
mmiosize = 0x400; // 1GB
reclaim = false;
@ -2071,7 +2073,7 @@ static void sdram_mmap_regs(struct sysinfo *s)
u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
reg8 &= ~0x7;
reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */
reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */
pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8);
printk(BIOS_DEBUG, "GBSM (igd) = verified %08x (written %08x)\n",

8
src/northbridge/intel/x4x/raminit_ddr23.c
View File

@ -1722,7 +1722,9 @@ static void configure_mmap(struct sysinfo *s)
ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);
gfxsize = ggc2uma[(ggc & 0xf0) >> 4];
gttsize = ggc2gtt[(ggc & 0xf00) >> 8];
tsegsize = 8; // 8MB TSEG
/* TSEG 2M, This amount can easily be covered by SMRR MTRR's,
which requires to have TSEG_BASE aligned to TSEG_SIZE. */
tsegsize = 2;
mmiosize = 0x800; // 2GB MMIO
umasizem = gfxsize + gttsize + tsegsize;
mmiostart = 0x1000 - mmiosize + umasizem;
@ -1759,10 +1761,10 @@ static void configure_mmap(struct sysinfo *s)
pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud);
pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20);
pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20);
/* Enable and set tseg size to 8M */
/* Enable and set tseg size to 2M */
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
reg8 &= ~0x7;
reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */
reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */
pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8);
pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20);
}