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mb/clevo/n130wu: Use device alias names in devicetree 

Switch to device alias names in devicetree. Remove unnecessary comments
since the names are self-explanatory.

Change-Id: Id486d9bd44bd7ba6a93a5f757af487b211e58efa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Felix Singer 2021-05-08 00:42:04 +02:00 committed by Patrick Georgi
parent 2b8d7216ef
commit d5245e03fa
1 changed files with 18 additions and 18 deletions
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36
src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
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@ -44,10 +44,10 @@ chip soc/intel/skylake
end end
device domain 0 on device domain 0 on
subsystemid 0x1558 0x1313 inherit subsystemid 0x1558 0x1313 inherit
device pci 00.0 on end # Host Bridge device ref system_agent on end
device pci 02.0 on end # Integrated Graphics Device device ref igpu on end
device pci 04.0 on end # SA thermal subsystem device ref sa_thermal on end
device pci 14.0 on # USB xHCI device ref south_xhci on
register "SsicPortEnable" = "0" register "SsicPortEnable" = "0"
# USB2 # USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, right register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, right
@ -63,19 +63,19 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C, right register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C, right
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left
end end
device pci 14.2 on end # Thermal Subsystem device ref thermal on end
device pci 16.0 on # Management Engine Interface 1 device ref heci1 on
register "HeciEnabled" = "1" register "HeciEnabled" = "1"
end end
device pci 17.0 on # SATA device ref sata on
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
# Ports # Ports
register "SataPortsEnable[0]" = "1" register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[2]" = "1" register "SataPortsEnable[2]" = "1"
register "SataPortsDevSlp[2]" = "1" register "SataPortsDevSlp[2]" = "1"
end end
device pci 19.0 on end # UART 2 device ref uart2 on end
device pci 1c.0 on # PCI Express Port 1 device ref pcie_rp1 on
device pci 00.0 on end # x4 TBT device pci 00.0 on end # x4 TBT
register "PcieRpEnable[0]" = "1" register "PcieRpEnable[0]" = "1"
register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqSupport[0]" = "1"
@ -85,7 +85,7 @@ chip soc/intel/skylake
register "PcieRpLtrEnable[0]" = "1" register "PcieRpLtrEnable[0]" = "1"
smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X"
end end
device pci 1c.4 on # PCI Express Port 5 device ref pcie_rp5 on
device pci 00.0 on end # x1 LAN device pci 00.0 on end # x1 LAN
register "PcieRpEnable[4]" = "1" register "PcieRpEnable[4]" = "1"
register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqSupport[4]" = "1"
@ -93,7 +93,7 @@ chip soc/intel/skylake
register "PcieRpClkSrcNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3"
register "PcieRpLtrEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1"
end end
device pci 1c.5 on # PCI Express Port 6 device ref pcie_rp6 on
device pci 00.0 on end # x1 WLAN device pci 00.0 on end # x1 WLAN
register "PcieRpEnable[5]" = "1" register "PcieRpEnable[5]" = "1"
register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqSupport[5]" = "1"
@ -102,7 +102,7 @@ chip soc/intel/skylake
register "PcieRpLtrEnable[5]" = "1" register "PcieRpLtrEnable[5]" = "1"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
end end
device pci 1d.0 on # PCI Express Port 9 device ref pcie_rp9 on
device pci 00.0 on end # x4 M.2/M (J_SSD1) device pci 00.0 on end # x4 M.2/M (J_SSD1)
register "PcieRpEnable[8]" = "1" register "PcieRpEnable[8]" = "1"
register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqSupport[8]" = "1"
@ -111,7 +111,7 @@ chip soc/intel/skylake
register "PcieRpLtrEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
end end
device pci 1f.0 on # LPC Interface device ref lpc_espi on
register "gen1_dec" = "0x000c0681" register "gen1_dec" = "0x000c0681"
register "gen2_dec" = "0x000c1641" register "gen2_dec" = "0x000c1641"
register "gen3_dec" = "0x00040069" register "gen3_dec" = "0x00040069"
@ -120,14 +120,14 @@ chip soc/intel/skylake
device pnp 0c31.0 on end device pnp 0c31.0 on end
end end
end end
device pci 1f.1 hidden end # P2SB device ref p2sb hidden end
device pci 1f.2 on # Power Management Controller device ref pmc on
register "gpe0_dw0" = "GPP_C" register "gpe0_dw0" = "GPP_C"
register "gpe0_dw1" = "GPP_D" register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E" register "gpe0_dw2" = "GPP_E"
end end
device pci 1f.3 on end # Intel HDA device ref hda on end
device pci 1f.4 on end # SMBus device ref smbus on end
device pci 1f.5 on end # PCH SPI device ref fast_spi on end
end end
end end