soc/intel/quark: Disable FSP serial output
Disable FSP output when CONFIG_DEFAULT_CONSOLE_LOGLEVEL is not set to 8 (BIOS_SPEW). Use the console log level to choose between the serial port address and NULL and pass it to FSP for the serial port address. TEST=Build and run on Galileo Gen2. Change-Id: I5498aad218524c211082d85d0ae9aacaf08a80f6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16005 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -120,7 +120,8 @@ void soc_memory_init_params(struct romstage_params *params,
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upd->RankMask = config->RankMask;
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upd->RmuBaseAddress = (uintptr_t)rmu_file;
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upd->RmuLength = rmu_file_len;
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upd->SerialPortBaseAddress = UART_BASE_ADDRESS;
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upd->SerialPortBaseAddress = console_log_level(BIOS_SPEW)
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? UART_BASE_ADDRESS : 0;
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upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
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config->SmmTsegSize : 0;
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upd->SocRdOdtVal = config->SocRdOdtVal;
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@ -161,7 +161,8 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *fspm_upd)
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upd->RankMask = config->RankMask;
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upd->RmuBaseAddress = (uintptr_t)rmu_file;
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upd->RmuLength = rmu_file_len;
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upd->SerialPortBaseAddress = UART_BASE_ADDRESS;
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upd->SerialPortBaseAddress = console_log_level(BIOS_SPEW)
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? UART_BASE_ADDRESS : 0;
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upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
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config->SmmTsegSize : 0;
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upd->SocRdOdtVal = config->SocRdOdtVal;
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