sb/intel/*: add option to lockdown chipset on normal boot path
On platforms with a PCH, some registers within host bridge should be locked down on each normal boot path (done by either coreboot or payload) and S3 resume (always done by coreboot). A function to perform such locking is implemented in src/northbridge/ intel/*/finalize.c, and is designed as the handler of an #SMI triggered with outb(APM_CNT_FINALIZE, APM_CNT), but currently this #SMI is only triggered during s3 resume, and not on normal boot path. This problem has beed discussed in https://mail.coreboot.org/pipermail/coreboot/2017-August/084924.html . This time, an option "INTEL_CHIPSET_LOCKDOWN" within src/southbridge/ intel/common/Kconfig is added to control the actual locking, which depends on several compatibility flags, including "HAVE_INTEL_CHIPSET_LOCKDOWN". In this commit, "ibexpeak", "bd82x6x", "fsp_bd82x6x", and "lynxpoint" have the flag "HAVE_INTEL_CHIPSET_LOCKDOWN" selected. The change is only well tested on Sandy Bridge, my Lenovo x230. Change-Id: I43d4142291c8737b29738c41e8c484328b297b55 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -39,6 +39,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
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select HAVE_INTEL_FIRMWARE
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select SOUTHBRIDGE_INTEL_COMMON_GPIO
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select RTC
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select HAVE_INTEL_CHIPSET_LOCKDOWN
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config EHCI_BAR
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hex
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@ -829,9 +829,12 @@ static void southbridge_fill_ssdt(device_t device)
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static void lpc_final(struct device *dev)
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{
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if (CONFIG_HAVE_SMI_HANDLER && acpi_is_wakeup_s3()) {
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/* Call SMM finalize() handlers before resume */
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outb(0xcb, 0xb2);
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/* Call SMM finalize() handlers before resume */
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if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
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if (IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN) ||
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acpi_is_wakeup_s3()) {
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outb(APM_CNT_FINALIZE, APM_CNT);
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}
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}
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}
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@ -4,3 +4,16 @@ config SOUTHBRIDGE_INTEL_COMMON_GPIO
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_SMBUS
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def_bool n
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config HAVE_INTEL_CHIPSET_LOCKDOWN
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def_bool n
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config INTEL_CHIPSET_LOCKDOWN
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depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS
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#ChromeOS's payload seems to handle finalization on its on.
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bool "Lock down chipset in coreboot"
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default y
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help
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Some registers within host bridge on particular chipsets should be
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locked down on each normal boot path (done by either coreboot or payload)
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and S3 resume (always done by coreboot). Select this to let coreboot
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to do this on normal boot path.
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@ -33,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
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select HAVE_INTEL_FIRMWARE
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select SOUTHBRIDGE_INTEL_COMMON
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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select HAVE_INTEL_CHIPSET_LOCKDOWN
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config EHCI_BAR
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hex
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@ -739,6 +739,17 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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fadt->x_gpe1_blk.addrh = 0x0;
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}
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static void lpc_final(struct device *dev)
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{
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/* Call SMM finalize() handlers before resume */
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if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
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if (IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN) ||
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acpi_is_wakeup_s3()) {
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outb(APM_CNT_FINALIZE, APM_CNT);
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}
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}
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}
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static struct pci_operations pci_ops = {
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.set_subsystem = set_subsystem,
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};
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@ -750,6 +761,7 @@ static struct device_operations device_ops = {
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.write_acpi_tables = acpi_write_hpet,
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.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
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.init = lpc_init,
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.final = lpc_final,
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.enable = pch_lpc_enable,
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.scan_bus = scan_lpc_bus,
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.ops_pci = &pci_ops,
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@ -36,6 +36,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
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select ACPI_SATA_GENERATOR
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select HAVE_INTEL_FIRMWARE
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select SOUTHBRIDGE_INTEL_COMMON_GPIO
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select HAVE_INTEL_CHIPSET_LOCKDOWN
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config EHCI_BAR
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hex
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@ -782,6 +782,17 @@ static void southbridge_fill_ssdt(device_t device)
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intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
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}
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static void lpc_final(struct device *dev)
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{
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/* Call SMM finalize() handlers before resume */
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if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
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if (IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN) ||
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acpi_is_wakeup_s3()) {
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outb(APM_CNT_FINALIZE, APM_CNT);
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}
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}
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}
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static struct pci_operations pci_ops = {
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.set_subsystem = set_subsystem,
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};
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@ -794,6 +805,7 @@ static struct device_operations device_ops = {
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.acpi_fill_ssdt_generator = southbridge_fill_ssdt,
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.write_acpi_tables = acpi_write_hpet,
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.init = lpc_init,
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.final = lpc_final,
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.enable = pch_lpc_enable,
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.scan_bus = scan_lpc_bus,
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.ops_pci = &pci_ops,
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@ -34,6 +34,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
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select HAVE_SPI_CONSOLE_SUPPORT
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select RTC
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select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP
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select HAVE_INTEL_CHIPSET_LOCKDOWN
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config INTEL_LYNXPOINT_LP
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bool
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@ -121,13 +121,13 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
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}
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/*
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* Finalize system before payload boot if not in ChromeOS environment.
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* Finalize system before payload boot if INTEL_CHIPSET_LOCKDOWN=y
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*/
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#if !IS_ENABLED(CONFIG_CHROMEOS)
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#if IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN)
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static void finalize_boot(void *unused)
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{
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outb(0xcb, 0xb2);
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outb(APM_CNT_FINALIZE, APM_CNT);
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}
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL);
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