intel/smm/gen1: Use smm_subregion()
Change-Id: I371ed41f485b3143e47f091681198d6674928897 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34740 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -43,10 +43,8 @@
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struct smm_relocation_params {
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u32 smram_base;
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u32 smram_size;
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u32 ied_base;
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u32 ied_size;
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uintptr_t ied_base;
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size_t ied_size;
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msr_t smrr_base;
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msr_t smrr_mask;
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};
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@ -103,50 +101,31 @@ static void write_smrr(struct smm_relocation_params *relo_params)
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static void fill_in_relocation_params(struct smm_relocation_params *params)
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{
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uintptr_t tseg_base;
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size_t tseg_size;
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/* All range registers are aligned to 4KiB */
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const u32 rmask = ~((1 << 12) - 1);
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const u32 tsegmb = northbridge_get_tseg_base();
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/* TSEG base is usually aligned down (to 8MiB). So we can't
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derive the TSEG size from the distance to GTT but use the
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configuration value instead. */
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const u32 tseg_size = northbridge_get_tseg_size();
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smm_region(&tseg_base, &tseg_size);
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params->smram_base = tsegmb;
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params->smram_size = tseg_size;
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if (CONFIG_IED_REGION_SIZE != 0) {
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ASSERT(params->smram_size > CONFIG_IED_REGION_SIZE);
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params->smram_size -= CONFIG_IED_REGION_SIZE;
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params->ied_base = tsegmb + tseg_size - CONFIG_IED_REGION_SIZE;
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params->ied_size = CONFIG_IED_REGION_SIZE;
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}
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/* Adjust available SMM handler memory size. */
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if (CONFIG(TSEG_STAGE_CACHE)) {
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ASSERT(params->smram_size > CONFIG_SMM_RESERVED_SIZE);
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params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
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}
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if (IS_ALIGNED(tsegmb, tseg_size)) {
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/* SMRR has 32-bits of valid address aligned to 4KiB. */
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struct cpuinfo_x86 c;
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/* On model_6fx and model_1067x bits [0:11] on smrr_base
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are reserved */
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get_fms(&c, cpuid_eax(1));
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if (cpu_has_alternative_smrr())
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params->smrr_base.lo = (params->smram_base & rmask);
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else
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params->smrr_base.lo = (params->smram_base & rmask)
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| MTRR_TYPE_WRBACK;
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params->smrr_base.hi = 0;
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params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
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| MTRR_PHYS_MASK_VALID;
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params->smrr_mask.hi = 0;
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} else {
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if (!IS_ALIGNED(tseg_base, tseg_size)) {
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printk(BIOS_WARNING,
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"TSEG base not aligned with TSEG SIZE! Not setting SMRR\n");
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return;
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}
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/* SMRR has 32-bits of valid address aligned to 4KiB. */
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params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
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params->smrr_base.hi = 0;
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params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
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params->smrr_mask.hi = 0;
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/* On model_6fx and model_1067x bits [0:11] on smrr_base are reserved */
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if (cpu_has_alternative_smrr())
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params->smrr_base.lo &= ~rmask;
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smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size);
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}
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static void setup_ied_area(struct smm_relocation_params *params)
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@ -186,11 +165,11 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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fill_in_relocation_params(&smm_reloc_params);
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if (CONFIG_IED_REGION_SIZE != 0)
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smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
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if (smm_reloc_params.ied_size)
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setup_ied_area(&smm_reloc_params);
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*perm_smbase = smm_reloc_params.smram_base;
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*perm_smsize = smm_reloc_params.smram_size;
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*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
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}
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@ -221,7 +200,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
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printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
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/* Make appropriate changes to the save state map. */
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if (CONFIG_IED_REGION_SIZE != 0)
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if (relo_params->ied_size)
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printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",
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smbase, iedbase);
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else
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@ -235,7 +214,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
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/* Write EMRR and SMRR MSRs based on indicated support. */
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mtrr_cap = rdmsr(MTRR_CAP_MSR);
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if (!(mtrr_cap.lo & SMRR_SUPPORTED && relo_params->smrr_mask.lo != 0))
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if (!(mtrr_cap.lo & SMRR_SUPPORTED))
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return;
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if (cpu_has_alternative_smrr())
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@ -23,8 +23,6 @@ struct ied_header {
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} __packed;
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/* These helpers are for performing SMM relocation. */
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u32 northbridge_get_tseg_base(void);
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u32 northbridge_get_tseg_size(void);
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void northbridge_write_smram(u8 smram);
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void smm_lock(void);
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@ -23,9 +23,9 @@
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#include <device/pci_def.h>
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#include <console/console.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <cbmem.h>
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#include <program_loading.h>
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#include <stage_cache.h>
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#include <cpu/intel/smm_reloc.h>
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#include "gm45.h"
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@ -84,7 +84,7 @@ u32 decode_tseg_size(u8 esmramc)
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}
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}
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u32 northbridge_get_tseg_base(void)
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static uintptr_t northbridge_get_tseg_base(void)
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{
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const pci_devfn_t dev = PCI_DEV(0, 0, 0);
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@ -107,7 +107,7 @@ u32 northbridge_get_tseg_base(void)
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return tor;
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}
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u32 northbridge_get_tseg_size(void)
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static size_t northbridge_get_tseg_size(void)
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{
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const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
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return decode_tseg_size(esmramc) << 10;
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@ -123,14 +123,10 @@ void *cbmem_top(void)
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return (void *) top_of_ram;
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}
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void stage_cache_external_region(void **base, size_t *size)
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void smm_region(uintptr_t *start, size_t *size)
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{
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/* The stage cache lives at the end of the TSEG region.
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* The top of RAM is defined to be the TSEG base address.
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*/
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*size = CONFIG_SMM_RESERVED_SIZE;
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*base = (void *)((uintptr_t)northbridge_get_tseg_base()
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+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
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*start = northbridge_get_tseg_base();
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*size = northbridge_get_tseg_size();
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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@ -22,10 +22,10 @@
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#include "i945.h"
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#include <console/console.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <program_loading.h>
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#include <cpu/intel/smm_reloc.h>
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#include <stdint.h>
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#include <stage_cache.h>
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/* Decodes TSEG region size to bytes. */
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u32 decode_tseg_size(const u8 esmramc)
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@ -45,7 +45,7 @@ u32 decode_tseg_size(const u8 esmramc)
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}
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}
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u32 northbridge_get_tseg_base(void)
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static uintptr_t northbridge_get_tseg_base(void)
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{
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uintptr_t tom;
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@ -60,7 +60,7 @@ u32 northbridge_get_tseg_base(void)
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return tom;
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}
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u32 northbridge_get_tseg_size(void)
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static size_t northbridge_get_tseg_size(void)
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{
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const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
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return decode_tseg_size(esmramc);
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@ -89,14 +89,10 @@ u32 decode_igd_memory_size(const u32 gms)
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return ggc2uma[gms] << 10;
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}
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void stage_cache_external_region(void **base, size_t *size)
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void smm_region(uintptr_t *start, size_t *size)
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{
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/* The stage cache lives at the end of the TSEG region.
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* The top of RAM is defined to be the TSEG base address.
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*/
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*size = CONFIG_SMM_RESERVED_SIZE;
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*base = (void *)((uintptr_t)northbridge_get_tseg_base()
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+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
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*start = northbridge_get_tseg_base();
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*size = northbridge_get_tseg_size();
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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@ -21,8 +21,8 @@
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#include <cbmem.h>
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#include <console/console.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <program_loading.h>
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#include <stage_cache.h>
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#include <cpu/intel/smm_reloc.h>
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#include "nehalem.h"
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@ -33,12 +33,12 @@ static uintptr_t smm_region_start(void)
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return tom;
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}
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u32 northbridge_get_tseg_base(void)
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static uintptr_t northbridge_get_tseg_base(void)
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{
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return (u32)smm_region_start();
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return smm_region_start();
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}
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u32 northbridge_get_tseg_size(void)
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static size_t northbridge_get_tseg_size(void)
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{
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return CONFIG_SMM_TSEG_SIZE;
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}
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return (void *) smm_region_start();
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}
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void stage_cache_external_region(void **base, size_t *size)
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void smm_region(uintptr_t *start, size_t *size)
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{
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/* The stage cache lives at the end of TSEG region.
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* The top of RAM is defined to be the TSEG base address. */
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*size = CONFIG_SMM_RESERVED_SIZE;
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*base = (void *)((uintptr_t)northbridge_get_tseg_base() +
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northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
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*start = northbridge_get_tseg_base();
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*size = northbridge_get_tseg_size();
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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@ -24,9 +24,9 @@
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#include <cbmem.h>
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#include <northbridge/intel/pineview/pineview.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <cpu/intel/smm_reloc.h>
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#include <stdint.h>
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#include <stage_cache.h>
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u8 decode_pciebar(u32 *const base, u32 *const len)
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{
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@ -116,13 +116,13 @@ static u32 decode_tseg_size(const u32 esmramc)
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}
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}
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u32 northbridge_get_tseg_size(void)
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static size_t northbridge_get_tseg_size(void)
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{
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const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
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return decode_tseg_size(esmramc);
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}
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u32 northbridge_get_tseg_base(void)
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static uintptr_t northbridge_get_tseg_base(void)
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{
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return pci_read_config32(PCI_DEV(0, 0, 0), TSEG);
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}
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@ -139,14 +139,10 @@ void *cbmem_top(void)
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}
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void stage_cache_external_region(void **base, size_t *size)
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void smm_region(uintptr_t *start, size_t *size)
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{
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/* The stage cache lives at the end of the TSEG region.
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* The top of RAM is defined to be the TSEG base address.
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*/
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*size = CONFIG_SMM_RESERVED_SIZE;
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*base = (void *)((uintptr_t)northbridge_get_tseg_base()
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+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
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*start = northbridge_get_tseg_base();
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*size = northbridge_get_tseg_size();
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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@ -21,8 +21,8 @@
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#include <console/console.h>
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#include <cpu/intel/smm_reloc.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <program_loading.h>
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#include <stage_cache.h>
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#include "sandybridge.h"
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static uintptr_t smm_region_start(void)
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return (void *) smm_region_start();
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}
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u32 northbridge_get_tseg_base(void)
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static uintptr_t northbridge_get_tseg_base(void)
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{
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return ALIGN_DOWN(smm_region_start(), 1*MiB);
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}
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u32 northbridge_get_tseg_size(void)
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static size_t northbridge_get_tseg_size(void)
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{
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return CONFIG_SMM_TSEG_SIZE;
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}
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void stage_cache_external_region(void **base, size_t *size)
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void smm_region(uintptr_t *start, size_t *size)
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{
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/* The stage cache lives at the end of TSEG region.
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* The top of RAM is defined to be the TSEG base address. */
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*size = CONFIG_SMM_RESERVED_SIZE;
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*base = (void *)((uintptr_t)northbridge_get_tseg_base() + northbridge_get_tseg_size()
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- CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE);
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*start = northbridge_get_tseg_base();
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*size = northbridge_get_tseg_size();
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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@ -25,10 +25,10 @@
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#include <device/pci_def.h>
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#include <console/console.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <program_loading.h>
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#include <cpu/intel/smm_reloc.h>
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#include <stage_cache.h>
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/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
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u32 decode_igd_memory_size(const u32 gms)
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@ -112,13 +112,13 @@ u8 decode_pciebar(u32 *const base, u32 *const len)
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return 1;
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}
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u32 northbridge_get_tseg_size(void)
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static size_t northbridge_get_tseg_size(void)
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{
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const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
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return decode_tseg_size(esmramc);
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}
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u32 northbridge_get_tseg_base(void)
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static uintptr_t northbridge_get_tseg_base(void)
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{
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return pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG);
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}
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return (void *) top_of_ram;
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}
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void stage_cache_external_region(void **base, size_t *size)
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void smm_region(uintptr_t *start, size_t *size)
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{
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/* The stage cache lives at the end of the TSEG region.
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* The top of RAM is defined to be the TSEG base address.
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*/
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*size = CONFIG_SMM_RESERVED_SIZE;
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*base = (void *)((uintptr_t)northbridge_get_tseg_base()
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+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
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*start = northbridge_get_tseg_base();
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*size = northbridge_get_tseg_size();
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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