From d555d6a88cf733f9f5a0a24694691a6901a81c73 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 28 Aug 2020 02:12:52 +0200 Subject: [PATCH] mb/google/zork/dalboz: move PCIe GPP clock setting to devicetree BUG=b:149970243 BRANCH=zork Change-Id: I0b31466c5a991b02cef3432942f8de45805fe546 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/44891 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- .../google/zork/variants/baseboard/devicetree_dalboz.cb | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index c7616020ff..42219d7a16 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -180,6 +180,15 @@ chip soc/amd/picasso register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" + # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader + register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[4]" = "GPP_CLK_OFF" + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + device cpu_cluster 0 on device lapic 0 on end end