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tegra132: Change memlayout to have PRERAM and POSTRAM CBFS Cache 

Instead of having unified CBFS_CACHE and limiting the POSTRAM Cache size, split
them into PRERAM and POSTRAM CBFS_CACHE.

BUG=None
BRANCH=None
TEST=Compiles successfully for both rush and ryu. Boots to kernel prompt on ryu.

Change-Id: I2a70df22fe5bae23e05cdf1b8a300369c7ccf87d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b93bc06de76cab0a1ec9a56e12c9a6942a430893
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Change-Id: Iab21ff5c7ca880b6bd18846e5d8d71c26dff56cf
Original-Reviewed-on: https://chromium-review.googlesource.com/231546
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9535
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Furquan Shaikh 2014-11-21 17:04:42 -08:00 committed by Patrick Georgi
parent b136d9f18c
commit d56abd7d7a
1 changed files with 2 additions and 1 deletions
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3
src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
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@ -33,7 +33,7 @@ SECTIONS
{ {
SRAM_START(0x40000000) SRAM_START(0x40000000)
PRERAM_CBMEM_CONSOLE(0x40000000, 8K) PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
CBFS_CACHE(0x40002000, 72K) PRERAM_CBFS_CACHE(0x40002000, 72K)
VBOOT2_WORK(0x40014000, 16K) VBOOT2_WORK(0x40014000, 16K)
STACK(0x40018000, 2K) STACK(0x40018000, 2K)
BOOTBLOCK(0x40019000, 20K) BOOTBLOCK(0x40019000, 20K)
@ -44,5 +44,6 @@ SECTIONS
SRAM_END(0x40040000) SRAM_END(0x40040000)
DRAM_START(0x80000000) DRAM_START(0x80000000)
POSTRAM_CBFS_CACHE(0x80100000, 1M)
RAMSTAGE(0x80200000, 256K) RAMSTAGE(0x80200000, 256K)
} }