This is (most of) the usb2 debug console code ripped out of
Uwe's version of yh_rest_of_patch.patch (13.02.07 - [PATCH] Rest of huge MCP55 patch). I dropped a lot of stuff, like broken indenting, removed copyright messages, and this printk_ram_* stuff (what the heck is this supposed to be) This codebase is really a mess. Further tarball contributions without a _CLEANED UP_ patch will be denied, especially if they are not from an up to date svn tree. Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu
Stefan Reinauer
parent
3f5411cfca
commit
d57241fab5
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@ -442,6 +442,11 @@ define CONFIG_CONSOLE_SERIAL8250
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export always
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comment "Log messages to 8250 uart based serial console"
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end
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define CONFIG_USBDEBUG_DIRECT
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default 0
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export always
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comment "Log messages to ehci debug port console"
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end
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define DEFAULT_CONSOLE_LOGLEVEL
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default 7
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export always
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@ -999,6 +1004,12 @@ define CONFIG_PCI_64BIT_PREF_MEM
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comment "allow PCI device get 4G above Region as pref mem"
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end
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define CONFIG_AGESA
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default 0
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export always
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comment "use AMD AGESA to init RAM instead of native code"
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end
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define CONFIG_VIDEO_MB
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default none
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export used
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@ -1,4 +1,5 @@
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uses CONFIG_CONSOLE_SERIAL8250
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uses CONFIG_USBDEBUG_DIRECT
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_CONSOLE_BTEXT
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uses CONFIG_CONSOLE_LOGBUF
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@ -9,6 +10,9 @@ object printk.o
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if CONFIG_CONSOLE_SERIAL8250
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driver uart8250_console.o
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end
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if CONFIG_USBDEBUG_DIRECT
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driver usbdebug_direct_console.o
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end
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if CONFIG_CONSOLE_VGA
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driver vga_console.o
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end
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@ -0,0 +1,58 @@
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#include <console/console.h>
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#include <usbdebug_direct.h>
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#include <pc80/mc146818rtc.h>
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struct ehci_debug_info dbg_info;
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void set_ehci_base(unsigned ehci_base)
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{
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unsigned diff;
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if(!dbg_info.ehci_debug) return;
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diff = dbg_info.ehci_caps - ehci_base;
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dbg_info.ehci_regs -= diff;
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dbg_info.ehci_debug -= diff;
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dbg_info.ehci_caps = ehci_base;
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}
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void set_ehci_debug(unsigned ehci_debug)
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{
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dbg_info.ehci_debug = ehci_debug;
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}
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unsigned get_ehci_debug(void)
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{
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return dbg_info.ehci_debug;
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}
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static void dbgp_init(void)
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{
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struct ehci_debug_info *dbg_infox;
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dbg_infox = (struct ehci_debug_info *)((CONFIG_LB_MEM_TOPK<<10) - sizeof (struct ehci_debug_info)); //in RAM
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memcpy(&dbg_info, dbg_infox, sizeof(struct ehci_debug_info) );
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}
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static void dbgp_tx_byte(unsigned char data)
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{
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if(dbg_info.ehci_debug)
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dbgp_bulk_write_x(&dbg_info,&data,1);
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}
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static unsigned char dbgp_rx_byte(void)
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{
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unsigned char data = 0xff;
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if(dbg_info.ehci_debug)
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dbgp_bulk_read_x(&dbg_info,&data,1);
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return data;
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}
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static int dbgp_tst_byte(void)
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{
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return dbg_info.ehci_debug;
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}
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static struct console_driver usbdebug_direct_console __console = {
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.init = dbgp_init,
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.tx_byte = dbgp_tx_byte,
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.rx_byte = dbgp_rx_byte,
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.tst_byte = dbgp_tst_byte,
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};
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@ -546,6 +546,8 @@ static void amd_set_name_string_f(device_t dev)
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extern void model_fxx_update_microcode(unsigned cpu_deviceid);
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int init_processor_name(void);
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static unsigned ehci_debug_addr;
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void model_fxx_init(device_t dev)
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{
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unsigned long i;
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@ -565,11 +567,21 @@ void model_fxx_init(device_t dev)
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}
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#endif
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#if CONFIG_USBDEBUG_DIRECT
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if(!ehci_debug_addr)
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ehci_debug_addr = get_ehci_debug();
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set_ehci_debug(0);
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#endif
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/* Turn on caching if we haven't already */
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x86_enable_cache();
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amd_setup_mtrrs();
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x86_mtrr_check();
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#if CONFIG_USBDEBUG_DIRECT
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set_ehci_debug(ehci_debug_addr);
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#endif
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/* Update the microcode */
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model_fxx_update_microcode(dev->device);
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@ -0,0 +1,132 @@
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#ifndef EHCI_H
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#define EHCI_H
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struct ehci_caps {
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/* these fields are specified as 8 and 16 bit registers,
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* but some hosts can't perform 8 or 16 bit PCI accesses.
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*/
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u32 hc_capbase;
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#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
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#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
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u32 hcs_params; /* HCSPARAMS - offset 0x4 */
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#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
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#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
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#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
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#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
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#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
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#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
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#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
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u32 hcc_params; /* HCCPARAMS - offset 0x8 */
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#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
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#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
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#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
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#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
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#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
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#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
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u8 portroute [8]; /* nibbles for routing - offset 0xC */
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} __attribute__ ((packed));
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/* Section 2.3 Host Controller Operational Registers */
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struct ehci_regs {
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/* USBCMD: offset 0x00 */
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u32 command;
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/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
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#define CMD_PARK (1<<11) /* enable "park" on async qh */
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#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
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#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
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#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
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#define CMD_ASE (1<<5) /* async schedule enable */
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#define CMD_PSE (1<<4) /* periodic schedule enable */
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/* 3:2 is periodic frame list size */
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#define CMD_RESET (1<<1) /* reset HC not bus */
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#define CMD_RUN (1<<0) /* start/stop HC */
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/* USBSTS: offset 0x04 */
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u32 status;
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#define STS_ASS (1<<15) /* Async Schedule Status */
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#define STS_PSS (1<<14) /* Periodic Schedule Status */
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#define STS_RECL (1<<13) /* Reclamation */
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#define STS_HALT (1<<12) /* Not running (any reason) */
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/* some bits reserved */
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/* these STS_* flags are also intr_enable bits (USBINTR) */
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#define STS_IAA (1<<5) /* Interrupted on async advance */
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#define STS_FATAL (1<<4) /* such as some PCI access errors */
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#define STS_FLR (1<<3) /* frame list rolled over */
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#define STS_PCD (1<<2) /* port change detect */
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#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
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#define STS_INT (1<<0) /* "normal" completion (short, ...) */
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/* USBINTR: offset 0x08 */
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u32 intr_enable;
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/* FRINDEX: offset 0x0C */
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u32 frame_index; /* current microframe number */
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/* CTRLDSSEGMENT: offset 0x10 */
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u32 segment; /* address bits 63:32 if needed */
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/* PERIODICLISTBASE: offset 0x14 */
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u32 frame_list; /* points to periodic list */
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/* ASYNCLISTADDR: offset 0x18 */
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u32 async_next; /* address of next async queue head */
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u32 reserved [9];
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/* CONFIGFLAG: offset 0x40 */
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u32 configured_flag;
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#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
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/* PORTSC: offset 0x44 */
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u32 port_status [0]; /* up to N_PORTS */
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/* 31:23 reserved */
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#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
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#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
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#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
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/* 19:16 for port testing */
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#define PORT_LED_OFF (0<<14)
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#define PORT_LED_AMBER (1<<14)
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#define PORT_LED_GREEN (2<<14)
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#define PORT_LED_MASK (3<<14)
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#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
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#define PORT_POWER (1<<12) /* true: has power (see PPC) */
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#define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */
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/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
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/* 9 reserved */
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#define PORT_RESET (1<<8) /* reset port */
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#define PORT_SUSPEND (1<<7) /* suspend port */
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#define PORT_RESUME (1<<6) /* resume it */
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#define PORT_OCC (1<<5) /* over current change */
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#define PORT_OC (1<<4) /* over current active */
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#define PORT_PEC (1<<3) /* port enable change */
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#define PORT_PE (1<<2) /* port enable */
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#define PORT_CSC (1<<1) /* connect status change */
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#define PORT_CONNECT (1<<0) /* device connected */
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#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
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} __attribute__ ((packed));
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/* Appendix C, Debug port ... intended for use with special "debug devices"
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* that can help if there's no serial console. (nonstandard enumeration.)
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*/
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struct ehci_dbg_port {
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u32 control;
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#define DBGP_OWNER (1<<30)
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#define DBGP_ENABLED (1<<28)
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#define DBGP_DONE (1<<16)
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#define DBGP_INUSE (1<<10)
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#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
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# define DBGP_ERR_BAD 1
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# define DBGP_ERR_SIGNAL 2
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#define DBGP_ERROR (1<<6)
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#define DBGP_GO (1<<5)
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#define DBGP_OUT (1<<4)
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#define DBGP_LEN(x) (((x)>>0)&0x0f)
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u32 pids;
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#define DBGP_PID_GET(x) (((x)>>16)&0xff)
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#define DBGP_PID_SET(data,tok) (((data)<<8)|(tok))
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u32 data03;
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u32 data47;
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u32 address;
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#define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep))
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} __attribute__ ((packed));
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#endif
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@ -0,0 +1,83 @@
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#ifndef USB_CH9_H
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#define USB_CH9_H
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#define USB_DIR_OUT 0 /* to device */
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#define USB_DIR_IN 0x80 /* to host */
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/*
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* USB types, the second of three bRequestType fields
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*/
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#define USB_TYPE_MASK (0x03 << 5)
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#define USB_TYPE_STANDARD (0x00 << 5)
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#define USB_TYPE_CLASS (0x01 << 5)
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#define USB_TYPE_VENDOR (0x02 << 5)
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#define USB_TYPE_RESERVED (0x03 << 5)
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/*
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* USB recipients, the third of three bRequestType fields
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*/
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#define USB_RECIP_MASK 0x1f
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#define USB_RECIP_DEVICE 0x00
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#define USB_RECIP_INTERFACE 0x01
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#define USB_RECIP_ENDPOINT 0x02
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#define USB_RECIP_OTHER 0x03
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/* From Wireless USB 1.0 */
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#define USB_RECIP_PORT 0x04
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#define USB_RECIP_RPIPE 0x05
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/*
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* Standard requests, for the bRequest field of a SETUP packet.
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*
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* These are qualified by the bRequestType field, so that for example
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* TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved
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* by a GET_STATUS request.
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*/
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#define USB_REQ_GET_STATUS 0x00
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#define USB_REQ_CLEAR_FEATURE 0x01
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#define USB_REQ_SET_FEATURE 0x03
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#define USB_REQ_SET_ADDRESS 0x05
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#define USB_REQ_GET_DESCRIPTOR 0x06
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#define USB_REQ_SET_DESCRIPTOR 0x07
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#define USB_REQ_GET_CONFIGURATION 0x08
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#define USB_REQ_SET_CONFIGURATION 0x09
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#define USB_REQ_GET_INTERFACE 0x0A
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#define USB_REQ_SET_INTERFACE 0x0B
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#define USB_REQ_SYNCH_FRAME 0x0C
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#define USB_REQ_SET_ENCRYPTION 0x0D /* Wireless USB */
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#define USB_REQ_GET_ENCRYPTION 0x0E
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#define USB_REQ_RPIPE_ABORT 0x0E
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#define USB_REQ_SET_HANDSHAKE 0x0F
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#define USB_REQ_RPIPE_RESET 0x0F
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#define USB_REQ_GET_HANDSHAKE 0x10
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#define USB_REQ_SET_CONNECTION 0x11
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#define USB_REQ_SET_SECURITY_DATA 0x12
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#define USB_REQ_GET_SECURITY_DATA 0x13
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#define USB_REQ_SET_WUSB_DATA 0x14
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#define USB_REQ_LOOPBACK_DATA_WRITE 0x15
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#define USB_REQ_LOOPBACK_DATA_READ 0x16
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#define USB_REQ_SET_INTERFACE_DS 0x17
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#define USB_DT_DEBUG 0x0a
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#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */
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//frim usb_ch9.h
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struct usb_ctrlrequest {
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uint8_t bRequestType;
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uint8_t bRequest;
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uint16_t wValue;
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uint16_t wIndex;
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uint16_t wLength;
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} __attribute__ ((packed));
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struct usb_debug_descriptor {
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uint8_t bLength;
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uint8_t bDescriptorType;
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/* bulk endpoints with 8 byte maxpacket */
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uint8_t bDebugInEndpoint;
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uint8_t bDebugOutEndpoint;
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};
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#endif
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@ -0,0 +1,17 @@
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#ifndef USBDEBUG_DIRECT_H
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#define USBDEBUG_DIRECT_H
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struct ehci_debug_info {
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void *ehci_caps;
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void *ehci_regs;
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void *ehci_debug;
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unsigned devnum;
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unsigned endpoint_out;
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unsigned endpoint_in;
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};
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extern int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size);
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extern int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size);
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extern void set_ehci_base(unsigned ehci_base);
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extern void set_ehci_debug(unsigned ehci_deug);
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extern unsigned get_ehci_debug(void);
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#endif
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@ -1,9 +1,15 @@
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uses HAVE_FALLBACK_BOOT
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uses CONFIG_USE_INIT
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uses CONFIG_USE_PRINTK_IN_CAR
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uses CONFIG_USBDEBUG_DIRECT
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object clog2.o
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object uart8250.o
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if CONFIG_USBDEBUG_DIRECT
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object usbdebug_direct.o
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end
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object memset.o
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object memcpy.o
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object memcmp.o
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|
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|
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@ -0,0 +1,539 @@
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/*
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* Copyright (C) 2006 Eric Biederman (ebiederm@xmission.com)
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*
|
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License version
|
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* 2 as published by the Free Software Foundation.
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*
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* 2006.12.10 yhlu moved it to LinuxBIOS and use struct instead
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*/
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#ifndef __ROMCC__
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#include <console/console.h>
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#else
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#if CONFIG_USE_PRINTK_IN_CAR==0
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#define printk_debug(fmt, arg...) do {} while(0)
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#endif
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#endif
|
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|
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#include <arch/io.h>
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#include <usb_ch9.h>
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#include <ehci.h>
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#include <usbdebug_direct.h>
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#define USB_DEBUG_DEVNUM 127
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#define DBGP_DATA_TOGGLE 0x8800
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#define DBGP_PID_UPDATE(x, tok) \
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((((x) ^ DBGP_DATA_TOGGLE) & 0xffff00) | ((tok) & 0xff))
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#define DBGP_LEN_UPDATE(x, len) (((x) & ~0x0f) | ((len) & 0x0f))
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/*
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* USB Packet IDs (PIDs)
|
||||
*/
|
||||
|
||||
/* token */
|
||||
#define USB_PID_OUT 0xe1
|
||||
#define USB_PID_IN 0x69
|
||||
#define USB_PID_SOF 0xa5
|
||||
#define USB_PID_SETUP 0x2d
|
||||
/* handshake */
|
||||
#define USB_PID_ACK 0xd2
|
||||
#define USB_PID_NAK 0x5a
|
||||
#define USB_PID_STALL 0x1e
|
||||
#define USB_PID_NYET 0x96
|
||||
/* data */
|
||||
#define USB_PID_DATA0 0xc3
|
||||
#define USB_PID_DATA1 0x4b
|
||||
#define USB_PID_DATA2 0x87
|
||||
#define USB_PID_MDATA 0x0f
|
||||
/* Special */
|
||||
#define USB_PID_PREAMBLE 0x3c
|
||||
#define USB_PID_ERR 0x3c
|
||||
#define USB_PID_SPLIT 0x78
|
||||
#define USB_PID_PING 0xb4
|
||||
#define USB_PID_UNDEF_0 0xf0
|
||||
|
||||
#define USB_PID_DATA_TOGGLE 0x88
|
||||
#define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE)
|
||||
|
||||
#define PCI_CAP_ID_EHCI_DEBUG 0xa
|
||||
|
||||
#define HUB_ROOT_RESET_TIME 50 /* times are in msec */
|
||||
#define HUB_SHORT_RESET_TIME 10
|
||||
#define HUB_LONG_RESET_TIME 200
|
||||
#define HUB_RESET_TIMEOUT 500
|
||||
|
||||
#define DBGP_MAX_PACKET 8
|
||||
|
||||
static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
|
||||
{
|
||||
unsigned ctrl;
|
||||
int loop = 0x100000;
|
||||
do {
|
||||
ctrl = readl(&ehci_debug->control);
|
||||
/* Stop when the transaction is finished */
|
||||
if (ctrl & DBGP_DONE)
|
||||
break;
|
||||
} while(--loop>0);
|
||||
|
||||
if (!loop) return -1000;
|
||||
|
||||
/* Now that we have observed the completed transaction,
|
||||
* clear the done bit.
|
||||
*/
|
||||
writel(ctrl | DBGP_DONE, &ehci_debug->control);
|
||||
return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
|
||||
}
|
||||
|
||||
static void dbgp_mdelay(int ms)
|
||||
{
|
||||
int i;
|
||||
while (ms--) {
|
||||
for (i = 0; i < 1000; i++)
|
||||
outb(0x1, 0x80);
|
||||
}
|
||||
}
|
||||
|
||||
static void dbgp_breath(void)
|
||||
{
|
||||
/* Sleep to give the debug port a chance to breathe */
|
||||
}
|
||||
|
||||
static int dbgp_wait_until_done(struct ehci_dbg_port *ehci_debug, unsigned ctrl)
|
||||
{
|
||||
unsigned pids, lpid;
|
||||
int ret;
|
||||
|
||||
int loop = 3;
|
||||
retry:
|
||||
writel(ctrl | DBGP_GO, &ehci_debug->control);
|
||||
ret = dbgp_wait_until_complete(ehci_debug);
|
||||
pids = readl(&ehci_debug->pids);
|
||||
lpid = DBGP_PID_GET(pids);
|
||||
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* If the port is getting full or it has dropped data
|
||||
* start pacing ourselves, not necessary but it's friendly.
|
||||
*/
|
||||
if ((lpid == USB_PID_NAK) || (lpid == USB_PID_NYET))
|
||||
dbgp_breath();
|
||||
|
||||
/* If I get a NACK reissue the transmission */
|
||||
if (lpid == USB_PID_NAK) {
|
||||
if (--loop > 0) goto retry;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void dbgp_set_data(struct ehci_dbg_port *ehci_debug, const void *buf, int size)
|
||||
{
|
||||
const unsigned char *bytes = buf;
|
||||
unsigned lo, hi;
|
||||
int i;
|
||||
lo = hi = 0;
|
||||
for (i = 0; i < 4 && i < size; i++)
|
||||
lo |= bytes[i] << (8*i);
|
||||
for (; i < 8 && i < size; i++)
|
||||
hi |= bytes[i] << (8*(i - 4));
|
||||
writel(lo, &ehci_debug->data03);
|
||||
writel(hi, &ehci_debug->data47);
|
||||
}
|
||||
|
||||
static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
|
||||
{
|
||||
unsigned char *bytes = buf;
|
||||
unsigned lo, hi;
|
||||
int i;
|
||||
lo = readl(&ehci_debug->data03);
|
||||
hi = readl(&ehci_debug->data47);
|
||||
for (i = 0; i < 4 && i < size; i++)
|
||||
bytes[i] = (lo >> (8*i)) & 0xff;
|
||||
for (; i < 8 && i < size; i++)
|
||||
bytes[i] = (hi >> (8*(i - 4))) & 0xff;
|
||||
}
|
||||
|
||||
static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, unsigned devnum, unsigned endpoint, const char *bytes, int size)
|
||||
{
|
||||
unsigned pids, addr, ctrl;
|
||||
int ret;
|
||||
if (size > DBGP_MAX_PACKET)
|
||||
return -1;
|
||||
|
||||
addr = DBGP_EPADDR(devnum, endpoint);
|
||||
|
||||
pids = readl(&ehci_debug->pids);
|
||||
pids = DBGP_PID_UPDATE(pids, USB_PID_OUT);
|
||||
|
||||
ctrl = readl(&ehci_debug->control);
|
||||
ctrl = DBGP_LEN_UPDATE(ctrl, size);
|
||||
ctrl |= DBGP_OUT;
|
||||
ctrl |= DBGP_GO;
|
||||
|
||||
dbgp_set_data(ehci_debug, bytes, size);
|
||||
writel(addr, &ehci_debug->address);
|
||||
writel(pids, &ehci_debug->pids);
|
||||
|
||||
ret = dbgp_wait_until_done(ehci_debug, ctrl);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size)
|
||||
{
|
||||
return dbgp_bulk_write(dbg_info->ehci_debug, dbg_info->devnum, dbg_info->endpoint_out, bytes, size);
|
||||
}
|
||||
|
||||
static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, unsigned devnum, unsigned endpoint, void *data, int size)
|
||||
{
|
||||
unsigned pids, addr, ctrl;
|
||||
int ret;
|
||||
|
||||
if (size > DBGP_MAX_PACKET)
|
||||
return -1;
|
||||
|
||||
addr = DBGP_EPADDR(devnum, endpoint);
|
||||
|
||||
pids = readl(&ehci_debug->pids);
|
||||
pids = DBGP_PID_UPDATE(pids, USB_PID_IN);
|
||||
|
||||
ctrl = readl(&ehci_debug->control);
|
||||
ctrl = DBGP_LEN_UPDATE(ctrl, size);
|
||||
ctrl &= ~DBGP_OUT;
|
||||
ctrl |= DBGP_GO;
|
||||
|
||||
writel(addr, &ehci_debug->address);
|
||||
writel(pids, &ehci_debug->pids);
|
||||
ret = dbgp_wait_until_done(ehci_debug, ctrl);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
if (size > ret)
|
||||
size = ret;
|
||||
dbgp_get_data(ehci_debug, data, size);
|
||||
return ret;
|
||||
}
|
||||
int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size)
|
||||
{
|
||||
return dbgp_bulk_read(dbg_info->ehci_debug, dbg_info->devnum, dbg_info->endpoint_in, data, size);
|
||||
}
|
||||
|
||||
static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requesttype, int request,
|
||||
int value, int index, void *data, int size)
|
||||
{
|
||||
unsigned pids, addr, ctrl;
|
||||
struct usb_ctrlrequest req;
|
||||
int read;
|
||||
int ret;
|
||||
|
||||
read = (requesttype & USB_DIR_IN) != 0;
|
||||
if (size > (read?DBGP_MAX_PACKET:0))
|
||||
return -1;
|
||||
|
||||
/* Compute the control message */
|
||||
req.bRequestType = requesttype;
|
||||
req.bRequest = request;
|
||||
req.wValue = value;
|
||||
req.wIndex = index;
|
||||
req.wLength = size;
|
||||
|
||||
pids = DBGP_PID_SET(USB_PID_DATA0, USB_PID_SETUP);
|
||||
addr = DBGP_EPADDR(devnum, 0);
|
||||
|
||||
ctrl = readl(&ehci_debug->control);
|
||||
ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req));
|
||||
ctrl |= DBGP_OUT;
|
||||
ctrl |= DBGP_GO;
|
||||
|
||||
/* Send the setup message */
|
||||
dbgp_set_data(ehci_debug, &req, sizeof(req));
|
||||
writel(addr, &ehci_debug->address);
|
||||
writel(pids, &ehci_debug->pids);
|
||||
ret = dbgp_wait_until_done(ehci_debug, ctrl);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
||||
/* Read the result */
|
||||
ret = dbgp_bulk_read(ehci_debug, devnum, 0, data, size);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ehci_reset_port(struct ehci_regs *ehci_regs, int port)
|
||||
{
|
||||
unsigned portsc;
|
||||
unsigned delay_time, delay;
|
||||
int loop;
|
||||
|
||||
/* Reset the usb debug port */
|
||||
portsc = readl(&ehci_regs->port_status[port - 1]);
|
||||
portsc &= ~PORT_PE;
|
||||
portsc |= PORT_RESET;
|
||||
writel(portsc, &ehci_regs->port_status[port - 1]);
|
||||
|
||||
delay = HUB_ROOT_RESET_TIME;
|
||||
for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
|
||||
delay_time += delay) {
|
||||
dbgp_mdelay(delay);
|
||||
|
||||
portsc = readl(&ehci_regs->port_status[port - 1]);
|
||||
if (portsc & PORT_RESET) {
|
||||
/* force reset to complete */
|
||||
loop = 2;
|
||||
writel(portsc & ~(PORT_RWC_BITS | PORT_RESET),
|
||||
&ehci_regs->port_status[port - 1]);
|
||||
do {
|
||||
dbgp_mdelay(delay);
|
||||
portsc = readl(&ehci_regs->port_status[port - 1]);
|
||||
delay_time += delay;
|
||||
} while ((portsc & PORT_RESET) && (--loop > 0));
|
||||
if (!loop) {
|
||||
printk_debug("ehci_reset_port forced done");
|
||||
}
|
||||
}
|
||||
|
||||
/* Device went away? */
|
||||
if (!(portsc & PORT_CONNECT))
|
||||
return -107;//-ENOTCONN;
|
||||
|
||||
/* bomb out completely if something weird happend */
|
||||
if ((portsc & PORT_CSC))
|
||||
return -22;//-EINVAL;
|
||||
|
||||
/* If we've finished resetting, then break out of the loop */
|
||||
if (!(portsc & PORT_RESET) && (portsc & PORT_PE))
|
||||
return 0;
|
||||
}
|
||||
return -16;//-EBUSY;
|
||||
}
|
||||
|
||||
static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port)
|
||||
{
|
||||
unsigned status;
|
||||
int ret, reps;
|
||||
for (reps = 0; reps < 3; reps++) {
|
||||
dbgp_mdelay(100);
|
||||
status = readl(&ehci_regs->status);
|
||||
if (status & STS_PCD) {
|
||||
ret = ehci_reset_port(ehci_regs, port);
|
||||
if (ret == 0)
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
return -107; //-ENOTCONN;
|
||||
}
|
||||
|
||||
|
||||
#define DBGP_DEBUG 1
|
||||
#if DBGP_DEBUG
|
||||
# define dbgp_printk printk_debug
|
||||
#else
|
||||
#define dbgp_printk(fmt, arg...) do {} while(0)
|
||||
#endif
|
||||
static void usbdebug_direct_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info)
|
||||
{
|
||||
struct ehci_caps *ehci_caps;
|
||||
struct ehci_regs *ehci_regs;
|
||||
struct ehci_dbg_port *ehci_debug;
|
||||
unsigned dbgp_endpoint_out;
|
||||
unsigned dbgp_endpoint_in;
|
||||
struct usb_debug_descriptor dbgp_desc;
|
||||
unsigned ctrl, devnum;
|
||||
int ret;
|
||||
unsigned delay_time, delay;
|
||||
int loop;
|
||||
|
||||
unsigned cmd, status, portsc, hcs_params, debug_port, n_ports, new_debug_port;
|
||||
int i;
|
||||
unsigned port_map_tried;
|
||||
|
||||
unsigned playtimes = 3;
|
||||
|
||||
ehci_caps = (struct ehci_caps *)ehci_bar;
|
||||
ehci_regs = (struct ehci_regs *)(ehci_bar + HC_LENGTH(readl(&ehci_caps->hc_capbase)));
|
||||
ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset);
|
||||
|
||||
info->ehci_debug = (void *)0;
|
||||
|
||||
try_next_time:
|
||||
port_map_tried = 0;
|
||||
|
||||
try_next_port:
|
||||
hcs_params = readl(&ehci_caps->hcs_params);
|
||||
debug_port = HCS_DEBUG_PORT(hcs_params);
|
||||
n_ports = HCS_N_PORTS(hcs_params);
|
||||
|
||||
dbgp_printk("debug_port: %d\n", debug_port);
|
||||
dbgp_printk("n_ports: %d\n", n_ports);
|
||||
|
||||
#if 0
|
||||
for (i = 1; i <= n_ports; i++) {
|
||||
portsc = readl(&ehci_regs->port_status[i-1]);
|
||||
dbgp_printk("portstatus%d: %08x\n", i, portsc);
|
||||
}
|
||||
#endif
|
||||
|
||||
if(port_map_tried && (new_debug_port!=debug_port)) {
|
||||
if(--playtimes) {
|
||||
set_debug_port(debug_port);
|
||||
goto try_next_time;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/* Reset the EHCI controller */
|
||||
loop = 10;
|
||||
cmd = readl(&ehci_regs->command);
|
||||
cmd |= CMD_RESET;
|
||||
writel(cmd, &ehci_regs->command);
|
||||
do {
|
||||
cmd = readl(&ehci_regs->command);
|
||||
} while ((cmd & CMD_RESET) && (--loop > 0));
|
||||
|
||||
if(!loop) {
|
||||
dbgp_printk("can not reset ehci\n");
|
||||
return;
|
||||
}
|
||||
dbgp_printk("ehci reset done\n");
|
||||
|
||||
/* Claim ownership, but do not enable yet */
|
||||
ctrl = readl(&ehci_debug->control);
|
||||
ctrl |= DBGP_OWNER;
|
||||
ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
|
||||
writel(ctrl, &ehci_debug->control);
|
||||
|
||||
/* Start the ehci running */
|
||||
cmd = readl(&ehci_regs->command);
|
||||
cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
|
||||
cmd |= CMD_RUN;
|
||||
writel(cmd, &ehci_regs->command);
|
||||
|
||||
/* Ensure everything is routed to the EHCI */
|
||||
writel(FLAG_CF, &ehci_regs->configured_flag);
|
||||
|
||||
/* Wait until the controller is no longer halted */
|
||||
loop = 10;
|
||||
do {
|
||||
status = readl(&ehci_regs->status);
|
||||
} while ((status & STS_HALT) && (--loop>0));
|
||||
|
||||
if(!loop) {
|
||||
dbgp_printk("ehci can be started\n");
|
||||
return;
|
||||
}
|
||||
dbgp_printk("ehci started\n");
|
||||
|
||||
/* Wait for a device to show up in the debug port */
|
||||
ret = ehci_wait_for_port(ehci_regs, debug_port);
|
||||
if (ret < 0) {
|
||||
dbgp_printk("No device found in debug port %d\n", debug_port);
|
||||
goto next_debug_port;
|
||||
}
|
||||
dbgp_printk("ehci wait for port done\n");
|
||||
|
||||
/* Enable the debug port */
|
||||
ctrl = readl(&ehci_debug->control);
|
||||
ctrl |= DBGP_CLAIM;
|
||||
writel(ctrl, &ehci_debug->control);
|
||||
ctrl = readl(&ehci_debug->control);
|
||||
if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
|
||||
dbgp_printk("No device in debug port\n");
|
||||
writel(ctrl & ~DBGP_CLAIM, &ehci_debug->control);
|
||||
goto err;
|
||||
}
|
||||
dbgp_printk("debug ported enabled\n");
|
||||
|
||||
/* Completely transfer the debug device to the debug controller */
|
||||
portsc = readl(&ehci_regs->port_status[debug_port - 1]);
|
||||
portsc &= ~PORT_PE;
|
||||
writel(portsc, &ehci_regs->port_status[debug_port - 1]);
|
||||
|
||||
dbgp_mdelay(100);
|
||||
|
||||
/* Find the debug device and make it device number 127 */
|
||||
for (devnum = 0; devnum <= 127; devnum++) {
|
||||
ret = dbgp_control_msg(ehci_debug, devnum,
|
||||
USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
|
||||
USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0,
|
||||
&dbgp_desc, sizeof(dbgp_desc));
|
||||
if (ret > 0)
|
||||
break;
|
||||
}
|
||||
if (devnum > 127) {
|
||||
dbgp_printk("Could not find attached debug device\n");
|
||||
goto err;
|
||||
}
|
||||
if (ret < 0) {
|
||||
dbgp_printk("Attached device is not a debug device\n");
|
||||
goto err;
|
||||
}
|
||||
dbgp_endpoint_out = dbgp_desc.bDebugOutEndpoint;
|
||||
dbgp_endpoint_in = dbgp_desc.bDebugInEndpoint;
|
||||
|
||||
/* Move the device to 127 if it isn't already there */
|
||||
if (devnum != USB_DEBUG_DEVNUM) {
|
||||
ret = dbgp_control_msg(ehci_debug, devnum,
|
||||
USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
|
||||
USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, (void *)0, 0);
|
||||
if (ret < 0) {
|
||||
dbgp_printk("Could not move attached device to %d\n",
|
||||
USB_DEBUG_DEVNUM);
|
||||
goto err;
|
||||
}
|
||||
devnum = USB_DEBUG_DEVNUM;
|
||||
dbgp_printk("debug device renamed to 127\n");
|
||||
}
|
||||
|
||||
/* Enable the debug interface */
|
||||
ret = dbgp_control_msg(ehci_debug, USB_DEBUG_DEVNUM,
|
||||
USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
|
||||
USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, (void *)0, 0);
|
||||
if (ret < 0) {
|
||||
dbgp_printk(" Could not enable the debug device\n");
|
||||
goto err;
|
||||
}
|
||||
dbgp_printk("debug interface enabled\n");
|
||||
|
||||
/* Perform a small write to get the even/odd data state in sync
|
||||
*/
|
||||
ret = dbgp_bulk_write(ehci_debug, USB_DEBUG_DEVNUM, dbgp_endpoint_out, " ",1);
|
||||
if (ret < 0) {
|
||||
dbgp_printk("dbgp_bulk_write failed: %d\n", ret);
|
||||
goto err;
|
||||
}
|
||||
dbgp_printk("small write doned\n");
|
||||
|
||||
info->ehci_caps = ehci_caps;
|
||||
info->ehci_regs = ehci_regs;
|
||||
info->ehci_debug = ehci_debug;
|
||||
info->devnum = devnum;
|
||||
info->endpoint_out = dbgp_endpoint_out;
|
||||
info->endpoint_in = dbgp_endpoint_in;
|
||||
|
||||
return;
|
||||
err:
|
||||
/* Things didn't work so remove my claim */
|
||||
ctrl = readl(&ehci_debug->control);
|
||||
ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
|
||||
writel(ctrl, &ehci_debug->control);
|
||||
|
||||
next_debug_port:
|
||||
port_map_tried |= (1<<(debug_port-1));
|
||||
if(port_map_tried != ((1<<n_ports) -1)) {
|
||||
new_debug_port = ((debug_port-1+1)%n_ports) + 1;
|
||||
set_debug_port(new_debug_port);
|
||||
goto try_next_port;
|
||||
}
|
||||
if(--playtimes) {
|
||||
set_debug_port(debug_port);
|
||||
goto try_next_time;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
#include <part/fallback_boot.h>
|
||||
#include "../lib/usbdebug_direct.c"
|
||||
static void early_usbdebug_direct_init(void)
|
||||
{
|
||||
struct ehci_debug_info *dbg_info =
|
||||
(struct ehci_debug_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - sizeof (struct ehci_debug_info));
|
||||
|
||||
usbdebug_direct_init(EHCI_BAR, EHCI_DEBUG_OFFSET, dbg_info);
|
||||
}
|
||||
void usbdebug_direct_tx_byte(unsigned char data)
|
||||
{
|
||||
struct ehci_debug_info *dbg_info;
|
||||
dbg_info = (struct ehci_debug_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - sizeof (struct ehci_debug_info)); // in Cache
|
||||
if (dbg_info->ehci_debug) {
|
||||
dbgp_bulk_write_x(dbg_info, &data, 1);
|
||||
}
|
||||
}
|
||||
void usbdebug_direct_ram_tx_byte(unsigned char data)
|
||||
{
|
||||
struct ehci_debug_info *dbg_info;
|
||||
dbg_info = (struct ehci_debug_info *)((CONFIG_LB_MEM_TOPK<<10) - sizeof (struct ehci_debug_info)); //in RAM
|
||||
if (dbg_info->ehci_debug) {
|
||||
dbgp_bulk_write_x(dbg_info, &data, 1);
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue