mainboard/intel/glkrvp: Add support for GLKRVP
GLKRVP is a reference board for GLK SOC RVP1 has DDR4 and RVP2 has LPDDR4 RVP2 is enabled by default and CONFIG_IS_GLK_RVP_1 should be selected if building for RVP1 GLKRVP can work with internal Intel EC or external Chrome EC AIC. For internal EC, CONFIG_EC_GOOGLE_CHROMEEC will not be selected ( CONFIG_GLK_INTEL_EC should be selected for internal EC config) By default, CONFIG_GLK_CHROME_EC is selected for external ChromeEC AIC config. Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef Reviewed-on: https://review.coreboot.org/19604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Hannah Williams
Aaron Durbin
parent
50ab84fa37
commit
d59f62bbda
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@ -0,0 +1,83 @@
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config BOARD_INTEL_BASEBOARD_GLKRVP
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def_bool n
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select SOC_INTEL_GLK
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_GENERIC
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select DRIVERS_PS2_KEYBOARD
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM2
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if BOARD_INTEL_BASEBOARD_GLKRVP
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config BASEBOARD_GLKRVP_LAPTOP
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def_bool n
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select SYSTEM_TYPE_LAPTOP
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choice GLK_EC
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prompt "ON BOARD EC"
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default GLK_CHROME_EC
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help
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This option allows you to select the on board EC to use.
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Select whether the board has Intel EC or Chrome EC
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config GLK_CHROME_EC
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bool "Chrome EC"
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_LPC
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config GLK_INTEL_EC
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bool "Intel EC"
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select EC_ACPI
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endchoice
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config CHROMEOS
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bool
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default y
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select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
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select VBOOT_LID_SWITCH
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config MAINBOARD_DIR
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string
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default intel/glkrvp
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config VARIANT_DIR
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string
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default "glkrvp" if BOARD_INTEL_GLKRVP
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config DEVICETREE
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string
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default "variants/baseboard/devicetree.cb"
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config MAINBOARD_PART_NUMBER
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string
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default "glkrvp" if BOARD_INTEL_GLKRVP
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config MAINBOARD_FAMILY
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string
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default "Intel_Glkrvp" if BOARD_INTEL_GLKRVP
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config GBB_HWID
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string
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depends on CHROMEOS
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default "GLKRVP TEST A-A 6939" if BOARD_INTEL_GLKRVP
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config MAX_CPUS
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int
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default 4
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config UART_FOR_CONSOLE
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int
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default 2
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config INCLUDE_NHLT_BLOBS
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bool "Include blobs for audio."
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config IS_GLK_RVP_1
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bool "Is this RVP1?"
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default n
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endif # BOARD_INTEL_GLKRVP
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@ -0,0 +1,4 @@
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config BOARD_INTEL_GLKRVP
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bool "Glkrvp"
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select BOARD_INTEL_BASEBOARD_GLKRVP
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select BASEBOARD_GLKRVP_LAPTOP
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@ -0,0 +1,20 @@
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bootblock-y += bootblock.c
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bootblock-y += ec.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-y += boardid.c
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ramstage-y += boardid.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-y += ec.c
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ramstage-y += mainboard.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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subdirs-y += variants/baseboard
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
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subdirs-y += variants/$(VARIANT_DIR)
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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@ -0,0 +1,3 @@
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/*
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* Blank file required by build system assumptions of this file being present.
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*/
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@ -0,0 +1,6 @@
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Vendor name: Intel
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Board name: Glkrvp GLK Reference Board
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Category: laptop
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -0,0 +1,38 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/variants.h>
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#include <boardid.h>
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#include <stddef.h>
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#include <ec/acpi/ec.h>
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#define BOARD_ID_GLK_RVP1_DDR4 0x5 /* RVP1 - DDR4 */
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#define BOARD_ID_GLK_RVP2_LP4SD 0x7 /* RVP2 - LP4 Solder Down */
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#define BOARD_ID_GLK_RVP2_LP4 0x8 /* RVP2 - LP4 Socket */
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#define EC_FAB_ID_CMD 0x0D /* Get the board fab ID in the lower 3 bits */
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uint8_t board_id(void)
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{
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MAYBE_STATIC int id = -1;
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if (id < 0) {
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if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
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id = variant_board_id();
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else {
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if (send_ec_command(EC_FAB_ID_CMD) == 0)
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id = (recv_ec_data() & 0x07);
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}
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}
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return id;
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}
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@ -0,0 +1,32 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2017 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/variants.h>
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#include <bootblock_common.h>
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#include <ec/ec.h>
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#include <soc/lpc.h>
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#include <soc/gpio.h>
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#include <variant/ec.h>
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void bootblock_mainboard_init(void)
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{
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const struct pad_config *pads;
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size_t num;
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lpc_configure_pads();
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pads = variant_early_gpio_table(&num);
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gpio_configure_pads(pads, num);
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mainboard_ec_init();
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}
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@ -0,0 +1,85 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2017 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/variants.h>
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#include <boot/coreboot_tables.h>
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#include <ec/google/chromeec/ec.h>
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#include <gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
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{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
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{-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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{GPIO_EC_IN_RW, ACTIVE_HIGH,
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gpio_get(GPIO_EC_IN_RW), "EC in RW"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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int get_lid_switch(void)
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{
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if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
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/* Read lid switch state from the EC. */
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return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
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else
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return 1;
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}
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int get_developer_mode_switch(void)
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{
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/* No physical developer mode switch. It's virtual. */
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return 0;
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}
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int get_recovery_mode_switch(void)
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{
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if (!IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
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return 0;
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/* Check if the EC has posted the keyboard recovery event. */
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return !!(google_chromeec_get_events_b() &
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
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}
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int clear_recovery_mode_switch(void)
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{
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if (!IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
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return 0;
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/* Clear keyboard recovery event. */
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return google_chromeec_clear_events_b(
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
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}
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int get_write_protect_state(void)
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{
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/* Read PCH_WP GPIO. */
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return gpio_get(GPIO_PCH_WP);
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}
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void mainboard_chromeos_acpi_generate(void)
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{
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const struct cros_gpio *gpios;
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size_t num;
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gpios = variant_cros_gpios(&num);
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chromeos_acpi_gpio_generate(gpios, num);
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}
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@ -0,0 +1,54 @@
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FLASH 16M {
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WP_RO@0x0 0x400000 {
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SI_DESC@0x0 0x1000
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IFWI@0x1000 0x1ff000
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RO_VPD@0x200000 0x4000
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RO_SECTION@0x204000 0x1fc000 {
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FMAP@0x0 0x800
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RO_FRID@0x800 0x40
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RO_FRID_PAD@0x840 0x7c0
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COREBOOT(CBFS)@0x1000 0x19b000
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GBB@0x19c000 0x40000
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RO_UNUSED@0x1dc000 0x20000
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}
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}
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MISC_RW@0x400000 0x4a000 {
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UNIFIED_MRC_CACHE@0x0 0x31000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x20000
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RW_VAR_MRC_CACHE@0x30000 0x1000
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}
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RW_ELOG@0x31000 0x4000
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RW_SHARED@0x35000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD@0x39000 0x2000
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TMP_UNUSED_HOLE@0x3B000 0xF000
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}
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RW_SECTION_A@0x44a000 0x477800 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x4677c0
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RW_FWID_A@0x4777c0 0x40
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}
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RW_SECTION_B@0x8c1800 0x477800 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x4677c0
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RW_FWID_B@0x4777c0 0x40
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}
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RW_NVRAM@0xd39000 0x6000
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RW_LEGACY(CBFS)@0xd3f000 0x200000
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BIOS_UNUSABLE@0xf3f000 0x40000
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DEVICE_EXTENSION@0xf7f000 0x80000
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# Currently, it is required that the BIOS region be a multiple of 8KiB.
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# This is required so that the recovery mechanism can find SIGN_CSE
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# region aligned to 4K at the center of BIOS region. Since the
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# descriptor at the beginning uses 4K and BIOS starts at an offset of
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# 4K, a hole of 4K is created towards the end of the flash to compensate
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# for the size requirement of BIOS region.
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# FIT tool thus creates descriptor with following regions:
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# Descriptor --> 0 to 4K
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# BIOS --> 4K to 0xf7f000
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# Device ext --> 0xf7f000 to 0xfff000
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UNUSED_HOLE@0xfff000 0x1000
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2017 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
|
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
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*/
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#include <variant/ec.h>
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#define GPE_EC_WAKE 0x26
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#define EC_SCI_GPI GPE0_DW1_05
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x05, // DSDT revision: ACPI v5.0
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20110725 // OEM revision
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)
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{
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/* global NVS and variables */
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#include <soc/intel/apollolake/acpi/globalnvs.asl>
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/* CPU */
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#include <soc/intel/apollolake/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/apollolake/acpi/northbridge.asl>
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#include <soc/intel/apollolake/acpi/southbridge.asl>
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#include <soc/intel/apollolake/acpi/pch_hda.asl>
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}
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}
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/* Chrome OS specific */
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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/* Chipset specific sleep states */
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#include <soc/intel/apollolake/acpi/sleepstates.asl>
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/* Chrome OS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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/* Dynamic Platform Thermal Framework */
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Scope (\_SB)
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{
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/* Per board variant specific definitions. */
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#include <variant/acpi/dptf.asl>
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/* Include soc specific DPTF changes */
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#include <soc/intel/apollolake/acpi/dptf.asl>
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/* Include common dptf ASL files */
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#include <soc/intel/common/acpi/dptf/dptf.asl>
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}
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#include "touchpad.asl"
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#include "touchpanel.asl"
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}
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@ -0,0 +1,80 @@
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/*
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* This file is part of the coreboot project.
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*
|
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* Copyright 2017 Intel Corp.
|
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*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <ec/ec.h>
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#include <ec/google/chromeec/ec.h>
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#include <rules.h>
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#include <soc/lpc.h>
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#include <variant/ec.h>
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static void ramstage_ec_init(void)
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{
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printk(BIOS_ERR, "mainboard: EC init\n");
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if (acpi_is_wakeup_s3()) {
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google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
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MAINBOARD_EC_S3_WAKE_EVENTS);
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/* Disable SMI and wake events */
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google_chromeec_set_smi_mask(0);
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/* Clear pending events */
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while (google_chromeec_get_event() != 0)
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;
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|
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/* Restore SCI event mask */
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google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
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} else {
|
||||
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
|
||||
MAINBOARD_EC_S5_WAKE_EVENTS);
|
||||
}
|
||||
|
||||
/* Clear wake event mask */
|
||||
google_chromeec_set_wake_mask(0);
|
||||
}
|
||||
|
||||
static void bootblock_ec_init(void)
|
||||
{
|
||||
uint16_t ec_ioport_base;
|
||||
size_t ec_ioport_size;
|
||||
/*
|
||||
* Set up LPC decoding for the ChromeEC I/O port ranges:
|
||||
* - Ports 62/66, 60/64, and 200->208
|
||||
* - ChromeEC specific communication I/O ports.
|
||||
*/
|
||||
lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | IOE_LGE_200);
|
||||
google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
|
||||
lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
|
||||
}
|
||||
|
||||
void mainboard_ec_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) {
|
||||
if (ENV_RAMSTAGE)
|
||||
ramstage_ec_init();
|
||||
else if (ENV_BOOTBLOCK)
|
||||
bootblock_ec_init();
|
||||
} else if (ENV_BOOTBLOCK)
|
||||
lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 |
|
||||
IOE_LGE_200);
|
||||
|
||||
if (IS_ENABLED(CONFIG_GLK_INTEL_EC)) {
|
||||
printk(BIOS_ERR, "S3 Hack Enable ACPI mode: outb(0xaa,0x66)\n");
|
||||
outb(0xaa, 0x66);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2017 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <boardid.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <ec/ec.h>
|
||||
#include <nhlt.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/nhlt.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
#include <variant/ec.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
static void mainboard_init(void *chip_info)
|
||||
{
|
||||
int boardid;
|
||||
const struct pad_config *pads;
|
||||
size_t num;
|
||||
|
||||
boardid = board_id();
|
||||
printk(BIOS_INFO, "Board ID: %d\n", boardid);
|
||||
|
||||
pads = variant_gpio_table(&num);
|
||||
gpio_configure_pads(pads, num);
|
||||
|
||||
mainboard_ec_init();
|
||||
}
|
||||
|
||||
static unsigned long mainboard_write_acpi_tables(
|
||||
device_t device, unsigned long current, acpi_rsdp_t *rsdp)
|
||||
{
|
||||
uintptr_t start_addr;
|
||||
uintptr_t end_addr;
|
||||
struct nhlt *nhlt;
|
||||
|
||||
start_addr = current;
|
||||
|
||||
nhlt = nhlt_init();
|
||||
|
||||
if (nhlt == NULL)
|
||||
return start_addr;
|
||||
|
||||
variant_nhlt_init(nhlt);
|
||||
|
||||
end_addr = nhlt_soc_serialize(nhlt, start_addr);
|
||||
|
||||
if (end_addr != start_addr)
|
||||
acpi_add_table(rsdp, (void *)start_addr);
|
||||
|
||||
return end_addr;
|
||||
}
|
||||
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
|
||||
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.init = mainboard_init,
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,239 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2017 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <string.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <boardid.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
#define BOARD_ID_GLK_RVP1_DDR4 0x5 /* GLK RVP1 - DDR4 */
|
||||
#define BOARD_ID_GLK_RVP2_LP4SD 0x7 /* GLK RVP2 - LP4 Solder Down */
|
||||
#define BOARD_ID_GLK_RVP2_LP4 0x8 /* RVP2 - LP4 Socket */
|
||||
|
||||
/* DDR4 specific swizzling data start */
|
||||
|
||||
/* Channel 0 PHY 0 to DUnit DQ mapping */
|
||||
static const uint8_t swizzling_ch0_ddr4[] = {
|
||||
15, 14, 10, 11, 8, 9, 13, 12, 2, 7, 3, 6, 4, 0, 1, 5,
|
||||
29, 31, 27, 26, 24, 28, 25, 30, 19, 22, 18, 21, 23, 16, 17, 20,
|
||||
};
|
||||
|
||||
/* Channel 1 PHY 0 to DUnit DQ mapping */
|
||||
static const uint8_t swizzling_ch1_ddr4[] = {
|
||||
1, 0, 4, 5, 7, 2, 6, 3, 24, 25, 28, 30, 26, 27, 31, 29,
|
||||
21, 20, 17, 16, 23, 22, 19, 18, 8, 12, 11, 15, 10, 9, 13, 14,
|
||||
};
|
||||
|
||||
/* Channel 1 PHY 1 to DUnit DQ mapping */
|
||||
static const uint8_t swizzling_ch2_ddr4[] = {
|
||||
14, 12, 9, 13, 10, 15, 11, 8, 1, 3, 7, 5, 2, 6, 0, 4,
|
||||
27, 24, 29, 28, 30, 26, 31, 25, 19, 20, 18, 22, 16, 21, 23, 17,
|
||||
};
|
||||
|
||||
/* Channel 0 PHY 1 to DUnit DQ mapping */
|
||||
static const uint8_t swizzling_ch3_ddr4[] = {
|
||||
12, 8, 13, 9, 15, 11, 14, 10, 0, 5, 1, 4, 7, 2, 6, 3,
|
||||
20, 16, 21, 17, 19, 18, 22, 23, 29, 24, 28, 26, 25, 30, 31, 27
|
||||
};
|
||||
/* DDR4 specific swizzling data end*/
|
||||
|
||||
/* LPDD4 specific swizzling data start */
|
||||
|
||||
/* Channel 0 PHY 0 to DUnit DQ mapping */
|
||||
static const uint8_t swizzling_ch0_lpddr4[] = {
|
||||
10, 8, 12, 11, 9, 13, 14, 15, 1, 3, 2, 0, 5, 4, 6, 7,
|
||||
30, 26, 24, 25, 28, 29, 31, 27, 20, 21, 22, 16, 23, 17, 18, 19,
|
||||
};
|
||||
|
||||
/* Channel 1 PHY 0 to DUnit DQ mapping */
|
||||
static const uint8_t swizzling_ch1_lpddr4[] = {
|
||||
0, 6, 7, 5, 3, 2, 1, 4, 12, 15, 13, 8, 9, 10, 11, 14,
|
||||
17, 18, 19, 16, 23, 20, 21, 22, 30, 31, 25, 27, 26, 29, 28, 24,
|
||||
};
|
||||
|
||||
/* Channel 1 PHY 1 to DUnit DQ mapping */
|
||||
static const uint8_t swizzling_ch2_lpddr4[] = {
|
||||
15, 8, 11, 10, 14, 12, 13, 9, 5, 1, 0, 6, 2, 3, 7, 4,
|
||||
31, 25, 24, 27, 30, 29, 28, 26, 21, 18, 20, 23, 16, 17, 22, 19,
|
||||
};
|
||||
|
||||
/* Channel 0 PHY 1 to DUnit DQ mapping */
|
||||
static const uint8_t swizzling_ch3_lpddr4[] = {
|
||||
15, 9, 8, 10, 13, 14, 12, 11, 7, 6, 5, 0, 4, 2, 1, 3,
|
||||
20, 21, 23, 22, 19, 17, 18, 16, 24, 27, 26, 30, 25, 31, 28, 29
|
||||
};
|
||||
/* LPDD4 specific swizzling data end */
|
||||
|
||||
static void fill_lpddr4_params(FSP_M_CONFIG *cfg)
|
||||
{
|
||||
cfg->Package = 1;
|
||||
cfg->MemoryDown = 1;
|
||||
cfg->DDR3LPageSize = 0;
|
||||
cfg->DDR3LASR = 0;
|
||||
cfg->ScramblerSupport = 1;
|
||||
cfg->ChannelHashMask = 0x36;
|
||||
cfg->SliceHashMask = 0x9;
|
||||
cfg->InterleavedMode = 2;
|
||||
cfg->ChannelsSlicesEnable = 0;
|
||||
cfg->MinRefRate2xEnable = 0;
|
||||
cfg->DualRankSupportEnable = 0;
|
||||
cfg->DisableFastBoot = 0;
|
||||
cfg->RmtMode = 0;
|
||||
cfg->RmtCheckRun = 0;
|
||||
cfg->RmtMarginCheckScaleHighThreshold = 0;
|
||||
cfg->MemorySizeLimit = 0;
|
||||
cfg->LowMemoryMaxValue = 0;
|
||||
cfg->HighMemoryMaxValue = 0;
|
||||
cfg->Profile = 7;
|
||||
cfg->DIMM0SPDAddress = 0x00;
|
||||
cfg->DIMM1SPDAddress = 0x00;
|
||||
cfg->Ch0_RankEnable = 0x1;
|
||||
cfg->Ch0_DeviceWidth = 0x1;
|
||||
cfg->Ch0_DramDensity = 0x2;
|
||||
cfg->Ch0_Option = 0x3;
|
||||
cfg->Ch0_TristateClk1 = 0;
|
||||
cfg->Ch0_Mode2N = 0;
|
||||
cfg->Ch0_OdtLevels = 0;
|
||||
cfg->Ch1_RankEnable = 0x1;
|
||||
cfg->Ch1_DeviceWidth = 0x1;
|
||||
cfg->Ch1_DramDensity = 0x2;
|
||||
cfg->Ch1_Option = 0x3;
|
||||
cfg->Ch1_TristateClk1 = 0;
|
||||
cfg->Ch1_Mode2N = 0;
|
||||
cfg->Ch1_OdtLevels = 0;
|
||||
cfg->Ch2_RankEnable = 0x1;
|
||||
cfg->Ch2_DeviceWidth = 0x1;
|
||||
cfg->Ch2_DramDensity = 0x2;
|
||||
cfg->Ch2_Option = 0x3;
|
||||
cfg->Ch2_TristateClk1 = 0;
|
||||
cfg->Ch2_Mode2N = 0;
|
||||
cfg->Ch2_OdtLevels = 0;
|
||||
cfg->Ch3_RankEnable = 0x1;
|
||||
cfg->Ch3_DeviceWidth = 0x1;
|
||||
cfg->Ch3_DramDensity = 0x2;
|
||||
cfg->Ch3_Option = 0x3;
|
||||
cfg->Ch3_TristateClk1 = 0;
|
||||
cfg->Ch3_Mode2N = 0;
|
||||
cfg->Ch3_OdtLevels = 0;
|
||||
/* phy0 ch0 */
|
||||
memcpy(cfg->Ch0_Bit_swizzling, swizzling_ch0_lpddr4,
|
||||
sizeof(swizzling_ch0_lpddr4));
|
||||
/* phy0 ch1 */
|
||||
memcpy(cfg->Ch1_Bit_swizzling, swizzling_ch1_lpddr4,
|
||||
sizeof(swizzling_ch1_lpddr4));
|
||||
/* phy1 ch1 */
|
||||
memcpy(cfg->Ch2_Bit_swizzling, swizzling_ch2_lpddr4,
|
||||
sizeof(swizzling_ch2_lpddr4));
|
||||
/* phy1 ch0 */
|
||||
memcpy(cfg->Ch3_Bit_swizzling, swizzling_ch3_lpddr4,
|
||||
sizeof(swizzling_ch3_lpddr4));
|
||||
}
|
||||
|
||||
static void fill_ddr4_params(FSP_M_CONFIG *cfg)
|
||||
{
|
||||
cfg->Package = 0; /* 0x1:BGA */
|
||||
cfg->MemoryDown = 0;
|
||||
cfg->DDR3LPageSize = 1;
|
||||
cfg->DDR3LASR = 0;
|
||||
cfg->ScramblerSupport = 0;
|
||||
cfg->ChannelHashMask = 0x36;
|
||||
cfg->SliceHashMask = 0x9;
|
||||
cfg->InterleavedMode = 0;
|
||||
cfg->ChannelsSlicesEnable = 0;
|
||||
cfg->MinRefRate2xEnable = 0;
|
||||
cfg->DualRankSupportEnable = 1;
|
||||
cfg->DisableFastBoot = 0;
|
||||
cfg->RmtMode = 0;
|
||||
cfg->RmtCheckRun = 0;
|
||||
cfg->RmtMarginCheckScaleHighThreshold = 0;
|
||||
cfg->MemorySizeLimit = 0;
|
||||
cfg->LowMemoryMaxValue = 0;
|
||||
cfg->HighMemoryMaxValue = 0;
|
||||
cfg->Profile = 11;
|
||||
cfg->DIMM0SPDAddress = 0xA0;
|
||||
cfg->DIMM1SPDAddress = 0xA4;
|
||||
cfg->Ch0_RankEnable = 0x3;
|
||||
cfg->Ch0_DeviceWidth = 0x1;
|
||||
cfg->Ch0_DramDensity = 0x0;
|
||||
cfg->Ch0_Option = 0x3; /* Bank Address Hashing enabled */
|
||||
cfg->Ch0_TristateClk1 = 0;
|
||||
cfg->Ch0_Mode2N = 0;
|
||||
cfg->Ch0_OdtLevels = 0;
|
||||
cfg->Ch1_RankEnable = 0x3;
|
||||
cfg->Ch1_DeviceWidth = 0x1;
|
||||
cfg->Ch1_DramDensity = 0x2;
|
||||
cfg->Ch1_Option = 0x3; /* Bank Address Hashing enabled */
|
||||
cfg->Ch1_TristateClk1 = 0;
|
||||
cfg->Ch1_Mode2N = 0;
|
||||
cfg->Ch1_OdtLevels = 0;
|
||||
cfg->Ch2_RankEnable = 0x0;
|
||||
cfg->Ch2_DeviceWidth = 0x1;
|
||||
cfg->Ch2_DramDensity = 0x2;
|
||||
cfg->Ch2_Option = 0x3; /* Bank Address Hashing enabled */
|
||||
cfg->Ch2_TristateClk1 = 0;
|
||||
cfg->Ch2_Mode2N = 0;
|
||||
cfg->Ch2_OdtLevels = 0;
|
||||
cfg->Ch3_RankEnable = 0x0;
|
||||
cfg->Ch3_DeviceWidth = 0x1;
|
||||
cfg->Ch3_DramDensity = 0x2;
|
||||
cfg->Ch3_Option = 0x3; /* Bank Address Hashing enabled */
|
||||
cfg->Ch3_TristateClk1 = 0;
|
||||
cfg->Ch3_Mode2N = 0;
|
||||
cfg->Ch3_OdtLevels = 0;
|
||||
|
||||
/* phy0 ch0 */
|
||||
memcpy(cfg->Ch0_Bit_swizzling, swizzling_ch0_ddr4,
|
||||
sizeof(swizzling_ch0_ddr4));
|
||||
/* phy0 ch1 */
|
||||
memcpy(cfg->Ch1_Bit_swizzling, swizzling_ch1_ddr4,
|
||||
sizeof(swizzling_ch1_ddr4));
|
||||
/* phy1 ch1 */
|
||||
memcpy(cfg->Ch2_Bit_swizzling, swizzling_ch2_ddr4,
|
||||
sizeof(swizzling_ch2_ddr4));
|
||||
/* phy1 ch0 */
|
||||
memcpy(cfg->Ch3_Bit_swizzling, swizzling_ch3_ddr4,
|
||||
sizeof(swizzling_ch3_ddr4));
|
||||
}
|
||||
|
||||
static void fill_memory_params(FSP_M_CONFIG *cfg)
|
||||
{
|
||||
uint8_t boardid;
|
||||
|
||||
if (IS_ENABLED(CONFIG_IS_GLK_RVP_1))
|
||||
boardid = BOARD_ID_GLK_RVP1_DDR4;
|
||||
else
|
||||
boardid = BOARD_ID_GLK_RVP2_LP4;
|
||||
|
||||
switch (boardid) {
|
||||
case BOARD_ID_GLK_RVP1_DDR4:
|
||||
fill_ddr4_params(cfg);
|
||||
break;
|
||||
case BOARD_ID_GLK_RVP2_LP4SD:
|
||||
case BOARD_ID_GLK_RVP2_LP4:
|
||||
fill_lpddr4_params(cfg);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
FSP_M_CONFIG *cfg = &memupd->FspmConfig;
|
||||
fill_memory_params(cfg);
|
||||
}
|
||||
|
||||
void mainboard_save_dimm_info(void)
|
||||
{
|
||||
save_lpddr4_dimm_info(variant_lpddr4_config(), variant_memory_sku());
|
||||
}
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2017 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <ec/google/chromeec/smm.h>
|
||||
#include <soc/pm.h>
|
||||
#include <soc/smm.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <variant/ec.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
void mainboard_smi_gpi_handler(const struct gpi_status *sts)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
|
||||
if (gpi_status_get(sts, EC_SMI_GPI))
|
||||
chromeec_smi_process_events();
|
||||
}
|
||||
|
||||
void mainboard_smi_sleep(u8 slp_typ)
|
||||
{
|
||||
const struct pad_config *pads;
|
||||
size_t num;
|
||||
|
||||
pads = variant_sleep_gpio_table(&num);
|
||||
gpio_configure_pads(pads, num);
|
||||
|
||||
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
|
||||
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
|
||||
MAINBOARD_EC_S5_WAKE_EVENTS);
|
||||
}
|
||||
|
||||
int mainboard_smi_apmc(u8 apmc)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
|
||||
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
|
||||
MAINBOARD_EC_SMI_EVENTS);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2017 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
Scope (\_SB.PCI0.I2C4)
|
||||
{
|
||||
Device (TPAD)
|
||||
{
|
||||
Name(_ADR, One)
|
||||
Name (_HID, "ALPS0001")
|
||||
Name (_CID, "PNP0C50")
|
||||
Name (_DDN, "ALPS Touchpad")
|
||||
Name (_UID, 1)
|
||||
Name (ISTP, 1) /* Touchpad */
|
||||
Name (_CRS, ResourceTemplate()
|
||||
{
|
||||
I2cSerialBus (
|
||||
0x2C, // SlaveAddress
|
||||
ControllerInitiated, // SlaveMode
|
||||
400000, // ConnectionSpeed
|
||||
AddressingMode7Bit, // AddressingMode
|
||||
"\\_SB.PCI0.I2C4", // ResourceSource
|
||||
)
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow)
|
||||
{
|
||||
GPIO_18_IRQ
|
||||
}
|
||||
GpioInt (Level, ActiveLow, ExclusiveAndWake, PullUp, 0x0000, "\\_SB.GPO1", 0x00, ResourceConsumer, ,)
|
||||
{
|
||||
18
|
||||
}
|
||||
})
|
||||
|
||||
Method (_STA)
|
||||
{
|
||||
Return (0xF)
|
||||
}
|
||||
Method(_DSM, 0x4, NotSerialized)
|
||||
{
|
||||
// DSM UUID for HIDI2C - HID driver does not load without DSM
|
||||
If(LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE")))
|
||||
{
|
||||
// Function 0 : Query Function
|
||||
If(LEqual(Arg2, Zero))
|
||||
{
|
||||
// Revision 1
|
||||
If(LEqual(Arg1, One))
|
||||
{
|
||||
Return (Buffer (One) {0x03})
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (Buffer (One) {0x00})
|
||||
}
|
||||
} ElseIf (LEqual(Arg2, One)) { // Function 1 : HID Function
|
||||
// HID Descriptor Address (IHV Specific)
|
||||
Return(0x0020)
|
||||
} Else {
|
||||
Return (Buffer (One) {0x00})
|
||||
}
|
||||
} Else {
|
||||
Return (Buffer (One) {0x00})
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2017 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
Scope(\_SB.PCI0.I2C7) {
|
||||
// Touch Panels on I2C7
|
||||
// GPIO_212:TCH_PNL_INTR_LS_N North Community, IRQ number 0x75.
|
||||
//------------------------
|
||||
Device (TPL1) {
|
||||
Name (HID2, 1)
|
||||
Name (_HID, "WCOM508E") // _HID: Hardware ID
|
||||
Name (_CID, "PNP0C50") // _CID: Compatible ID
|
||||
Name (_S0W, 0x04) // _S0W: S0 Device Wake State
|
||||
Name (SBFB, ResourceTemplate () {
|
||||
I2cSerialBus (
|
||||
0x000A,
|
||||
ControllerInitiated,
|
||||
1000000,
|
||||
AddressingMode7Bit,
|
||||
"\\_SB.PCI0.I2C7",
|
||||
0x00,
|
||||
ResourceConsumer,
|
||||
,
|
||||
)
|
||||
})
|
||||
//
|
||||
// GLK: Touchpanel Interrupt: GPIO_212: Northwest
|
||||
// Pin 77
|
||||
// Direct IRQ 0x75
|
||||
//
|
||||
Name (SBFG, ResourceTemplate () {
|
||||
GpioInt (Level, ActiveLow, Exclusive, PullUp, 0x0000,
|
||||
"\\_SB.GPO0", 0x00, ResourceConsumer, ,
|
||||
)
|
||||
{
|
||||
77
|
||||
}
|
||||
})
|
||||
Name (SBFI, ResourceTemplate () {
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
|
||||
{
|
||||
0x75,
|
||||
}
|
||||
})
|
||||
|
||||
Method (_INI, 0, NotSerialized) // _INI: Initialize
|
||||
{
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized) // _STA: Status
|
||||
{
|
||||
Return (0x0F)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized) {
|
||||
Return (ConcatenateResTemplate(SBFB, SBFG))
|
||||
}
|
||||
} // Device (TPL0)
|
||||
}
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
bootblock-y += gpio.c
|
||||
|
||||
romstage-y += boardid.c
|
||||
romstage-y += memory.c
|
||||
|
||||
ramstage-y += boardid.c
|
||||
ramstage-y += gpio.c
|
||||
ramstage-y += nhlt.c
|
||||
|
||||
smm-y += gpio.c
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2017 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
|
||||
uint8_t __attribute__((weak)) variant_board_id(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
|
||||
return google_chromeec_get_board_version();
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,148 @@
|
|||
chip soc/intel/apollolake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
# Disable unused clkreq of PCIe root ports
|
||||
register "pcie_rp1_clkreq_pin" = "3" # wifi/bt
|
||||
register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
register "pcie_rp4_clkreq_pin" = "1"
|
||||
register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
|
||||
|
||||
# GPIO for PERST_0
|
||||
# If the Board has PERST_0 signal, assign the GPIO
|
||||
# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
|
||||
register "prt0_gpio" = "GPIO_PRT0_UDEF"
|
||||
|
||||
# GPIO for SD card detect
|
||||
register "sdcard_cd_gpio" = "GPIO_186"
|
||||
|
||||
# EMMC TX DATA Delay 1
|
||||
# Refer to EDS-Vol2-22.3.
|
||||
# [14:8] steps of delay for HS400, each 125ps.
|
||||
# [6:0] steps of delay for SDR104/HS200, each 125ps.
|
||||
register "emmc_tx_data_cntl1" = "0x0C3A"
|
||||
|
||||
# EMMC TX DATA Delay 2
|
||||
# Refer to EDS-Vol2-22.3.
|
||||
# [30:24] steps of delay for SDR50, each 125ps.
|
||||
# [22:16] steps of delay for DDR50, each 125ps.
|
||||
# [14:8] steps of delay for SDR25/HS50, each 125ps.
|
||||
# [6:0] steps of delay for SDR12, each 125ps.
|
||||
register "emmc_tx_data_cntl2" = "0x28272929"
|
||||
|
||||
# EMMC RX CMD/DATA Delay 1
|
||||
# Refer to EDS-Vol2-22.3.
|
||||
# [30:24] steps of delay for SDR50, each 125ps.
|
||||
# [22:16] steps of delay for DDR50, each 125ps.
|
||||
# [14:8] steps of delay for SDR25/HS50, each 125ps.
|
||||
# [6:0] steps of delay for SDR12, each 125ps.
|
||||
register "emmc_rx_cmd_data_cntl1" = "0x003B263B"
|
||||
|
||||
# EMMC RX CMD/DATA Delay 2
|
||||
# Refer to EDS-Vol2-22.3.
|
||||
# [17:16] stands for Rx Clock before Output Buffer
|
||||
# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
|
||||
# [6:0] steps of delay for HS200, each 125ps.
|
||||
register "emmc_rx_cmd_data_cntl2" = "0x10008"
|
||||
|
||||
register "emmc_rx_strobe_cntl" = "0x0a0a"
|
||||
register "emmc_tx_cmd_cntl" = "0x1305"
|
||||
|
||||
# Enable DPTF
|
||||
register "dptf_enable" = "1"
|
||||
|
||||
# PL1 override 12000 mW: the energy calculation is wrong with the
|
||||
# current VR solution. Experiments show that SoC TDP max (6W) can
|
||||
# be reached when RAPL PL1 is set to 12W.
|
||||
register "tdp_pl1_override_mw" = "12000"
|
||||
# Set RAPL PL2 to 15W.
|
||||
register "tdp_pl2_override_mw" = "15000"
|
||||
|
||||
# Enable Audio Clock and Power gating
|
||||
register "hdaudio_clk_gate_enable" = "1"
|
||||
register "hdaudio_pwr_gate_enable" = "1"
|
||||
register "hdaudio_bios_config_lockdown" = "1"
|
||||
|
||||
# Enable lpss s0ix
|
||||
register "lpss_s0ix_enable" = "1"
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route, i.e., if this route changes then the affected GPE
|
||||
# offset bits also need to be changed. This sets the PMC register
|
||||
# GPE_CFG fields.
|
||||
#PMC_GPE_NW_63_32 - 03
|
||||
#PMC_GPE_N_95_64 - 08
|
||||
#PMC_GPE_NW_31_0 - 02
|
||||
register "gpe0_dw1" = "PMC_GPE_NW_63_32"
|
||||
register "gpe0_dw2" = "PMC_GPE_N_95_64"
|
||||
register "gpe0_dw3" = "PMC_GPE_NW_31_0"
|
||||
|
||||
# Enable I2C2 bus early for TPM access
|
||||
register "i2c[2].early_init" = "1"
|
||||
|
||||
# Minimum SLP S3 assertion width 28ms.
|
||||
register "slp_s3_assertion_width_usecs" = "28000"
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # - Host Bridge
|
||||
device pci 00.1 on end # - DPTF
|
||||
device pci 00.2 on end # - NPK
|
||||
device pci 02.0 on end # - Gen
|
||||
device pci 03.0 on end # - Iunit
|
||||
device pci 0c.0 on end # - CNVi
|
||||
device pci 0d.0 on end # - P2SB
|
||||
device pci 0d.1 on end # - PMC
|
||||
device pci 0d.2 on end # - SPI
|
||||
device pci 0d.3 on end # - Shared SRAM
|
||||
device pci 0e.0 on end # - Audio
|
||||
device pci 0f.0 on end # - Heci1
|
||||
device pci 0f.1 on end # - Heci2
|
||||
device pci 0f.2 on end # - Heci3
|
||||
device pci 11.0 off end # - ISH
|
||||
device pci 12.0 on end # - SATA
|
||||
device pci 13.0 off end # - PCIe-A 0 Slot 1
|
||||
device pci 13.1 off end # - PCIe-A 1
|
||||
device pci 13.2 on end # - PCIe-A 2 Onboard Lan
|
||||
device pci 13.3 off end # - PCIe-A 3
|
||||
device pci 14.0 off end # - PCIe-B 0 Slot2
|
||||
device pci 14.1 on end # - PCIe-B 1 Onboard M2 Slot(Wifi/BT)
|
||||
device pci 15.0 on end # - XHCI
|
||||
device pci 15.1 off end # - XDCI
|
||||
device pci 16.0 on end # - I2C 0
|
||||
device pci 16.1 off end # - I2C 1
|
||||
device pci 16.2 off end # - I2C 2
|
||||
device pci 16.3 off end # - I2C 3
|
||||
device pci 17.0 on end # - I2C 4
|
||||
device pci 17.1 off end # - I2C 5
|
||||
device pci 17.2 off end # - I2C 6
|
||||
device pci 17.3 on end # - I2C 7
|
||||
device pci 18.0 on end # - UART 0
|
||||
device pci 18.1 off end # - UART 1
|
||||
device pci 18.2 on end # - UART 2
|
||||
device pci 18.3 off end # - UART 3
|
||||
device pci 19.0 on end # - SPI 0
|
||||
device pci 19.1 on end # - SPI 1
|
||||
device pci 19.2 on end # - SPI 2
|
||||
device pci 1a.0 on end # - PWM
|
||||
device pci 1b.0 on end # - SDCARD
|
||||
device pci 1c.0 on end # - eMMC
|
||||
device pci 1e.0 off end # - SDIO
|
||||
device pci 1f.0 on # - LPC
|
||||
chip drivers/pc80/tpm
|
||||
register "irq_polarity" = "2"
|
||||
device pnp 0c31.0 on
|
||||
irq 0x70 = 10
|
||||
end
|
||||
end
|
||||
chip ec/google/chromeec
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end # - SMBUS
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,296 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2017 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <commonlib/helpers.h>
|
||||
|
||||
/*
|
||||
* Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
|
||||
* table found in EDS vol 1, but some pins aren't grouped functionally in
|
||||
* the table so those were moved for more logical grouping.
|
||||
*/
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* NORTHWEST COMMUNITY GPIOS */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_0, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TCK */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_1, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TRST_B */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_2, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TMS */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_3, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDI */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_4, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDO */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_5, UP_20K, DEEP, NF1, IGNORE, ENPU), /* JTAGX */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_6, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PREQ_B */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_7, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PRDY_B */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_CLK_VNN */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA0_VNN */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA1_VNN */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_11, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA2_VNN */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA3_VNN */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_13, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA4_VNN */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_14, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA5_VNN */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_15, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA6_VNN */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_16, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA7_VNN */
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_17, 1, DEEP, UP_20K, TxDRxE, SAME),/*Ec-to-SOC CS Wake */
|
||||
PAD_CFG_GPI_APIC_IOS(GPIO_18, UP_20K, DEEP, LEVEL, NONE, IGNORE, SAME),/* Touch Pad Interrupt */
|
||||
PAD_CFG_GPI_APIC_IOS(GPIO_19, UP_20K, DEEP, EDGE_SINGLE, NONE, TxDRxE, SAME),/*PMIC Interrupt*/
|
||||
PAD_CFG_GPI_APIC_IOS(GPIO_20, NONE, DEEP, LEVEL, NONE, IGNORE, SAME),/* Audio Codec Interrupt*/
|
||||
PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */
|
||||
PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */
|
||||
PAD_CFG_GPO_GPIO_DRIVER(GPIO_24, 1, DEEP, DN_20K),
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_25, 1, DEEP, UP_20K, TxLASTRxE, SAME),/*WWAN /RF_KILL_GPS*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/* NFC Interrupt */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_27, UP_20K, DEEP, NF2, TxLASTRxE, DISPUPD),/* RF_KILL_WiFi/WiFi_Disable */
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_28, 1, DEEP, UP_20K, TxLASTRxE, DISPUPD),/* RF_KILL_BT/BT_Disable */
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_29, 1, DEEP, UP_20K, HIZCRx0, DISPUPD),/* Codec Power Down: Ouput/ISH_GPIO_3*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_30, DN_20K, DEEP, NF1), /* ISH_GPIO_4 */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_31, DN_20K, DEEP, NF1), /* ISH_GPIO_5 */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_32, DN_20K, DEEP, NF1), /* ISH_GPIO_6 */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_33, DN_20K, DEEP, NF1), /* ISH_GPIO_7 */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_34, DN_20K, DEEP, NF1), /* ISH_GPIO_8/SUSCLK2 (1.8V) */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_35, UP_20K, DEEP, NF6), /* BSSB_CLK */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_36, UP_20K, DEEP, NF6), /* BSSB_DI */
|
||||
PAD_CFG_GPI_SCI_IOS(GPIO_37, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME),/*Runtime SCI */
|
||||
PAD_CFG_GPI_SCI_IOS(GPIO_38, UP_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME),/*Wake SCI */
|
||||
PAD_CFG_GPI_APIC_IOS(GPIO_39, DN_20K, DEEP, LEVEL, NONE, IGNORE, SAME),/* Finger Print Sensor Interrupt (DRDY) */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_40, UP_20K, DEEP, NF6),/*IERR (USB Camera Power Enable)*/
|
||||
PAD_CFG_GPI_SMI_IOS(GPIO_41, UP_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME),/*SOC_EXTSMI_N */
|
||||
PAD_CFG_NF(GPIO_42, DN_20K, DEEP, NF1), /* GP_INTD_DSI_TE1 */
|
||||
PAD_CFG_NF(GPIO_43, DN_20K, DEEP, NF1), /* GP_INTD_DSI_TE2 */
|
||||
PAD_CFG_NF(GPIO_44, UP_20K, DEEP, NF1), /* USB_OC0_B */
|
||||
PAD_CFG_NF(GPIO_45, UP_20K, DEEP, NF1), /* USB_OC1_B */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, DN_20K, DEEP, NF1, HIZCRx1, ENPU), /* DSI_I2C_SDA */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_47, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* DSI_I2C_SCL */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, UP_1K, DEEP, NF1), /* PMC_I2C_SDA */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, UP_1K, DEEP, NF1), /* PMC_I2C_SCL */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C0_SDA - Audio Codec*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C0_SCL - Audio Codec */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C1_SDA - NFC */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C1_SCL - NFC */
|
||||
PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_54, UP_20K, DEEP, HIZCRx1, ENPU),/*LPSS_I2C2_SDA*/
|
||||
PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_55, UP_20K, DEEP, HIZCRx1, ENPU),/*LPSS_I2C2_SCL*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* I2C3-SDA - DBG (PSS, SINAI2, MIPI) */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*I2C3-SCL - DBG (PSS, SINAI2, MIPI) */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_58, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*I2C4-SDA - Touch Pad*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_59, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*I2C4-SCL - Touch Pad*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-RXD - M.2dGNSS */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-TXD - M.2dGNSS */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_62, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-RTS_B - M.2 dGNSS */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_63, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-CTS_B - M.2 dGNSS */
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPSS_UART2_RXD*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),/*LPSS_UART2_TXD*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, TxDRxE, DISPUPD),/*RF_KILL_WWAN */
|
||||
#if IS_ENABLED(CONFIG_TPM_ON_FAST_SPI)
|
||||
PAD_CFG_GPI_INT(GPIO_67, UP_20K, DEEP, LEVEL),/*SPI TPM Interrupt */
|
||||
#endif
|
||||
PAD_CFG_NF(GPIO_68, UP_20K, DEEP, NF1),/*PMC_SPI_FS0*/
|
||||
PAD_CFG_GPI_APIC(GPIO_69, DN_20K, DEEP, EDGE_SINGLE, NONE),/*SIM Detect*/
|
||||
PAD_CFG_NF(GPIO_70, DN_20K, DEEP, NF1),/*PMC_SPI_FS2*/
|
||||
PAD_CFG_NF(GPIO_71, DN_20K, DEEP, NF1),/*PMC_SPI_RXD*/
|
||||
PAD_CFG_NF(GPIO_72, DN_20K, DEEP, NF1),/*PMC_SPI_TXD*/
|
||||
PAD_CFG_NF(GPIO_73, DN_20K, DEEP, NF1),/*PMC_SPI_CLK*/
|
||||
PAD_CFG_NF(GPIO_74, DN_20K, DEEP, NF1),/*THERMTRIP_B*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_75, UP_20K, DEEP, NF1, HIZCRx1),/*PROCHOT_B*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_211, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC_RST_B*/
|
||||
PAD_CFG_GPI_GPIO_DRIVER(GPIO_212, UP_20K, DEEP),/*Touch Panel Int*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 1, DEEP, NONE, HIZCRx0, SAME),/*DNX LED - CSE owned*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_214, 1, DEEP, NONE, HIZCRx0, SAME),/*LAN Isolate*/
|
||||
/* NORTH COMMUNITY GPIOS */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_76, UP_20K, DEEP, NF1),/*SVID Alert*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_77, UP_20K, DEEP, NF1),/* SVID Data */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_78, UP_20K, DEEP, NF1),/* SVID Clk */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_79, NATIVE, DEEP, NF1),/* Finger Print Sensor */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_80, NATIVE, DEEP, NF1),/* Finger Print Sensor CS */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_81, NONE, DEEP, NF3),/* FST_SPI_CS2_B - TPM */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_82, NATIVE, DEEP, NF1),/* Finger Print Sensor */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_83, NATIVE, DEEP, NF1),/* Finger Print Sensor */
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_84, NONE, DEEP, NF3, HIZCRx1),/* SPI iTouch*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_85, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch CS*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_86, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_87, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_88, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_89, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_90, NATIVE, DEEP, NF1),/*Function 1: FST SPI Boot Flash CS*/
|
||||
PAD_CFG_GPIO_HI_Z(GPIO_91, NATIVE, DEEP, IGNORE, SAME),/*FST_SPI_CS1_B*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_92, DN_20K, DEEP, NF1),/*FST_SPI_MOSI_IO0*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_93, NATIVE, DEEP, NF1),/*FST_SPI_MISO_IO1*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_94, NATIVE, DEEP, NF1),/*FST_SPI_IO2*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_95, NATIVE, DEEP, NF1),/*FST_SPI_IO3*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_96, NATIVE, DEEP, NF1),/*FST_SPI_CLK*/
|
||||
PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1),/*FST_SPI_CLK_FB*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_98, NONE, DEEP, NF1),/*PMU_PLTRST_B*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_99, UP_20K, DEEP, NF1),/*PMU_PWRBTN_B*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/*PMU_SLP_S0_B*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/*PMU_SLP_S3_B*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/*PMU_SLP_S4_B*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/*SUSPWRDNACK*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_104, UP_20K, DEEP, NF1),/*EMMC_DNX_PWR_EN_B*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, DN_20K, IGNORE, SAME),/*x4 Slot-2 Reset*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_106, UP_20K, DEEP, NF1),/*PMU_BATLOW_B*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_107, UP_20K, DEEP, NF1),/*PMU_RESETBUTTON_B*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_108, NONE, DEEP, NF1),/*PMU_SUSCLK*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_109, NONE, DEEP, NF1),/*SUS_STAT_B*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C5_SDA*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C5_SCL*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C6_SDA*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C6_SCL*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*LPSS_I2C7_SDA*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*LPSS_I2C7_SCL*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_116, UP_20K, DEEP, NF1),/*PCIE_WAKE0_B*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_117, UP_20K, DEEP, NF1),/*PCIE_WAKE1_B*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_118, UP_20K, DEEP, NF1),/*PCIE_WAKE2_B*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_119, UP_20K, DEEP, NF1),/*PCIE_WAKE3_B*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ0_B*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ1_B*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ2_B*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_123, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ3_B*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_124, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SDA*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_125, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SCL*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_126, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI1_DDC_SDA*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_127, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI1_DDC_SCL*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_128, DN_20K, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_VDDEN*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_129, DN_20K, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTEN*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_130, DN_20K, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTCTL*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_131, UP_20K, DEEP, NF1, TxDRxE ),/*HV_DDI0_HPD*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_132, UP_20K, DEEP, NF1, TxDRxE ),/*HV_DDI1_HPD*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_133, UP_20K, DEEP, NF1, TxDRxE ),/*HV_EDP_HPD*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_134, 1, DEEP, UP_20K, IGNORE, SAME),/*Slot-1 Power Enable*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_135, 1, DEEP, UP_20K, IGNORE, SAME),/*Slot-2 Power Enable*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_136, 1, DEEP, DN_20K, IGNORE, SAME),/*DGPU Power Select*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_137, 1, DEEP, UP_20K, IGNORE, SAME),/*slot-1 Reset*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_138, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/*SATA_GP0 (DC RTD3 need)*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_139, UP_20K, DEEP, NF2, TxLASTRxE, DISPUPD),/*SATA_GP1 (ZPODD_DEV_DET)*/
|
||||
PAD_CFG_NF(GPIO_140, UP_20K, DEEP, NF5),/*SATA_DEVSLP0 (DC DEV SLP)*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_141, UP_20K, DEEP, NF5, HIZCRx1),/*SATA_DEVSLP1 (ZPODD DEV ATN)*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_142, UP_20K, DEEP, NF5, HIZCRx1),/*SATA_LED*/
|
||||
PAD_CFG_GPI_APIC_IOS(GPIO_143, DN_20K, DEEP, LEVEL, NONE, HIZCRx1, SAME),/*DGPU Power Ok*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_144, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_VDDEN*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_145, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTEN*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_146, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTCTL*/
|
||||
PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1),/*LPC_ILB_SERIRQ*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_CLKOUT0*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_149, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_CLKOUT1*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_150, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_AD0*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_AD1*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_152, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_AD2*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_153, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_AD3*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_154, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_CLKRUNB*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_FRAMEB*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_157, 1, DEEP, UP_20K, IGNORE, SAME),/*WWAN_Reset/dGPS Reset*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_158, 0, DEEP, DN_20K, IGNORE, SAME),/*NFC_DFU*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_159, 1, DEEP, UP_20K, TxDRxE, ENPD),/*NFC reset*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_160, 1, DEEP, UP_20K, IGNORE, SAME),/*MDSI reset*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, IGNORE, SAME),/*Touch panel reset*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_162, 1, DEEP, UP_20K, IGNORE, SAME),/*AVS_I2S1_BCLK*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_163, 1, DEEP, UP_20K, IGNORE, SAME),/*M.2 WiFi Reset*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 1, DEEP, UP_20K, TxDRxE, ENPD),/*Touch Panel Power Enable*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_165, 1, DEEP, UP_20K, IGNORE, SAME),/*WWAN PWR EN/Full card power off*/
|
||||
|
||||
/* AUDIO COMMUNITY GPIOS*/
|
||||
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_166, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_HDA_BCLK*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_167, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_HDA_WS_SYNC*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_168, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_HDA_SDI*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_169, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_HDA_SDO*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_170, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_HDA_RSTB*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_171, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_M_CLK_A1*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_M_CLK_B1*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_173, DN_20K, DEEP, NF1, HIZCRx1, ENPD),/*AVS_M_DATA_1*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_174, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_M_CLK_AB2*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, DN_20K, DEEP, NF1, HIZCRx1, ENPD),/*AVS_M_DATA_2*/
|
||||
|
||||
/* SCC COMMUNITY GPIOS */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_176, UP_20K, DEEP, NF1),/*SMB_ALERTB*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_177, UP_20K, DEEP, NF1),/*SMB_CLK*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_178, UP_20K, DEEP, NF1),/*SMB_DATA*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_187, DN_20K, DEEP, NF1),/*SDCARD_LVL_WP*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_179, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD),/*SDCARD_CLK*/
|
||||
PAD_CFG_NF(GPIO_180, DN_20K, DEEP, NF1),/*SDCARD_CLK_FB*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_181, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D0*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_182, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D1*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_183, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D2*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_184, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D3*/
|
||||
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_185, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_CMD*/
|
||||
PAD_CFG_NF(GPIO_186, NONE, DEEP, NF1),/*SDCARD_CD_B*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_188, 0, DEEP, NONE, TxDRxE, SAME),/*SD Card*/
|
||||
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_210, 1, DEEP, UP_20K, HIZCRx0, DISPUPD),
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_189, DN_20K, DEEP, NF1, HIZCRx0),/*OSC_CLK_OUT_0*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_190, DN_20K, DEEP, NF1, HIZCRx0),/*OSC_CLK_OUT_1*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1),/*CNV_BRI_DT*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1),/*CNV_BRI_RSP*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1),/*CNV_RGI_DT*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1),/*CNV_RGI_RSP*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1),/*CNV_RF_RESET_B*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_196, NONE, DEEP, NF1),/*XTAL_CLKREQ*/
|
||||
PAD_CFG_NF(GPIO_197, DN_20K, DEEP, NF1),/*SDIO_CLK_FB*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0),/*EMMC0_CLK*/
|
||||
PAD_CFG_NF(GPIO_199, DN_20K, DEEP, NF1),/*EMMC0_CLK_FB*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D0*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D1*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D2*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D3*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D4*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D5*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D6*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D7*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_CMD*/
|
||||
PAD_CFG_NF_IOSSTATE(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0),/*EMMC0_STROBE*/
|
||||
};
|
||||
|
||||
const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
/* GPIOs needed prior to ramstage. */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_177, UP_20K, DEEP, NF1), /* SMB_CLK */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_178, UP_20K, DEEP, NF1), /* SMB_DATA */
|
||||
};
|
||||
|
||||
const struct pad_config * __attribute__((weak))
|
||||
variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
/* GPIO settings before entering sleep. */
|
||||
static const struct pad_config sleep_gpio_table[] = {
|
||||
#if 0
|
||||
PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */
|
||||
PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */
|
||||
#endif
|
||||
};
|
||||
|
||||
const struct pad_config * __attribute__((weak))
|
||||
variant_sleep_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(sleep_gpio_table);
|
||||
return sleep_gpio_table;
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
#if 0
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME),
|
||||
CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME),
|
||||
#endif
|
||||
};
|
||||
|
||||
const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(cros_gpios);
|
||||
return cros_gpios;
|
||||
}
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2017 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define DPTF_CPU_PASSIVE 80
|
||||
#define DPTF_CPU_CRITICAL 90
|
||||
#define DPTF_CPU_ACTIVE_AC0 90
|
||||
#define DPTF_CPU_ACTIVE_AC1 80
|
||||
#define DPTF_CPU_ACTIVE_AC2 70
|
||||
#define DPTF_CPU_ACTIVE_AC3 60
|
||||
#define DPTF_CPU_ACTIVE_AC4 50
|
||||
|
||||
#define DPTF_TSR0_SENSOR_ID 0
|
||||
#define DPTF_TSR0_SENSOR_NAME "Battery"
|
||||
#define DPTF_TSR0_PASSIVE 48
|
||||
#define DPTF_TSR0_CRITICAL 70
|
||||
|
||||
#define DPTF_TSR1_SENSOR_ID 1
|
||||
#define DPTF_TSR1_SENSOR_NAME "Ambient"
|
||||
#define DPTF_TSR1_PASSIVE 60
|
||||
#define DPTF_TSR1_CRITICAL 70
|
||||
|
||||
#define DPTF_TSR2_SENSOR_ID 2
|
||||
#define DPTF_TSR2_SENSOR_NAME "Charger"
|
||||
#define DPTF_TSR2_PASSIVE 55
|
||||
#define DPTF_TSR2_CRITICAL 100
|
||||
|
||||
#define DPTF_ENABLE_CHARGER
|
||||
|
||||
/* Charger performance states, board-specific values from charger and EC */
|
||||
Name (CHPS, Package () {
|
||||
Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
|
||||
Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
|
||||
Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
|
||||
Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
|
||||
Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
|
||||
})
|
||||
|
||||
Name (DTRT, Package () {
|
||||
/* CPU Throttle Effect on CPU */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 0 */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
|
||||
|
||||
#ifdef DPTF_ENABLE_CHARGER
|
||||
/* Charger Effect on Temp Sensor 1 */
|
||||
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
|
||||
#endif
|
||||
|
||||
/* CPU Effect on Temp Sensor 1 */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 2 */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
|
||||
})
|
||||
|
||||
Name (MPPC, Package ()
|
||||
{
|
||||
0x2, /* Revision */
|
||||
Package () { /* Power Limit 1 */
|
||||
0, /* PowerLimitIndex, 0 for Power Limit 1 */
|
||||
1600, /* PowerLimitMinimum */
|
||||
12000, /* PowerLimitMaximum */
|
||||
1000, /* TimeWindowMinimum */
|
||||
1000, /* TimeWindowMaximum */
|
||||
200 /* StepSize */
|
||||
},
|
||||
Package () { /* Power Limit 2 */
|
||||
1, /* PowerLimitIndex, 1 for Power Limit 2 */
|
||||
6000, /* PowerLimitMinimum */
|
||||
8000, /* PowerLimitMaximum */
|
||||
1000, /* TimeWindowMinimum */
|
||||
1000, /* TimeWindowMaximum */
|
||||
1000 /* StepSize */
|
||||
}
|
||||
})
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2017 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef BASEBOARD_EC_H
|
||||
#define BASEBOARD_EC_H
|
||||
|
||||
#include <ec/google/chromeec/ec_commands.h>
|
||||
|
||||
#define MAINBOARD_EC_SCI_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU))
|
||||
|
||||
#define MAINBOARD_EC_SMI_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
|
||||
|
||||
/* EC can wake from S5 with lid or power button */
|
||||
#define MAINBOARD_EC_S5_WAKE_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
|
||||
|
||||
/* EC can wake from S3 with lid or power button or key press */
|
||||
#define MAINBOARD_EC_S3_WAKE_EVENTS \
|
||||
(MAINBOARD_EC_S5_WAKE_EVENTS |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
|
||||
|
||||
/* Log EC wake events plus EC shutdown events */
|
||||
#define MAINBOARD_EC_LOG_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
|
||||
|
||||
/*
|
||||
* ACPI related definitions for ASL code.
|
||||
*/
|
||||
|
||||
/* Enable EC backed ALS device in ACPI */
|
||||
#define EC_ENABLE_ALS_DEVICE
|
||||
|
||||
/* Enable LID switch and provide wake pin for EC */
|
||||
#define EC_ENABLE_LID_SWITCH
|
||||
#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
|
||||
|
||||
/* Enable EC backed PD MCU device in ACPI */
|
||||
#define EC_ENABLE_PD_MCU_DEVICE
|
||||
|
||||
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
|
||||
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
|
||||
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2017 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef BASEBOARD_GPIO_H
|
||||
#define BASEBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/*
|
||||
* GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
|
||||
* which is North community
|
||||
*/
|
||||
#define EC_SCI_GPI GPE0_DW1_05
|
||||
|
||||
/* EC SMI */
|
||||
#define EC_SMI_GPI GPIO_41
|
||||
|
||||
#define GPE_EC_WAKE GPE0_DW1_06
|
||||
|
||||
/* Write Protect and indication if EC is in RW code. */
|
||||
#define GPIO_PCH_WP GPIO_75
|
||||
#define GPIO_EC_IN_RW GPIO_41
|
||||
|
||||
/* Memory SKU GPIOs. */
|
||||
#define MEM_CONFIG3 GPIO_45
|
||||
#define MEM_CONFIG2 GPIO_38
|
||||
#define MEM_CONFIG1 GPIO_102
|
||||
#define MEM_CONFIG0 GPIO_101
|
||||
|
||||
#endif /* BASEBOARD_GPIO_H */
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2017 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef BASEBOARD_VARIANTS_H
|
||||
#define BASEBOARD_VARIANTS_H
|
||||
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <stdint.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
/* Return the board id for the current variant board. */
|
||||
uint8_t variant_board_id(void);
|
||||
|
||||
/* The next set of functions return the gpio table and fill in the number of
|
||||
* entries for each table. */
|
||||
const struct pad_config *variant_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_sleep_gpio_table(size_t *num);
|
||||
|
||||
/* Baseboard default swizzle. Can be reused if swizzle is same. */
|
||||
extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle;
|
||||
/* Return LPDDR4 configuration structure. */
|
||||
const struct lpddr4_cfg *variant_lpddr4_config(void);
|
||||
/* Return memory SKU for the board. */
|
||||
size_t variant_memory_sku(void);
|
||||
|
||||
/* Return ChromeOS gpio table and fill in number of entries. */
|
||||
const struct cros_gpio *variant_cros_gpios(size_t *num);
|
||||
|
||||
/* Seed the NHLT tables with the board specific information. */
|
||||
struct nhlt;
|
||||
void variant_nhlt_init(struct nhlt *nhlt);
|
||||
|
||||
#endif /* BASEBOARD_VARIANTS_H */
|
||||
|
|
@ -0,0 +1,144 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2017 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <gpio.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = {
|
||||
/* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */
|
||||
.phys[LP4_PHYS_CH0A] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH0B] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH1A] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH1B] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 },
|
||||
},
|
||||
};
|
||||
|
||||
static const struct lpddr4_sku skus[] = {
|
||||
/*
|
||||
* K4F6E304HB-MGCJ - both logical channels While the parts
|
||||
* are listed at 16Gb there are 2 ranks per channel so indicate
|
||||
* the density as 8Gb per rank.
|
||||
*/
|
||||
[0] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "K4F6E304HB-MGCJ",
|
||||
},
|
||||
/* K4F8E304HB-MGCJ - both logical channels */
|
||||
[1] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "K4F8E304HB-MGCJ",
|
||||
},
|
||||
/*
|
||||
* MT53B512M32D2NP-062WT:C - both logical channels. While the parts
|
||||
* are listed at 16Gb there are 2 ranks per channel so indicate
|
||||
* the density as 8Gb per rank.
|
||||
*/
|
||||
[2] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "MT53B512M32D2NP",
|
||||
.disable_periodic_retraining = 1,
|
||||
},
|
||||
/* MT53B256M32D1NP-062 WT:C - both logical channels */
|
||||
[3] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "MT53B256M32D1NP",
|
||||
.disable_periodic_retraining = 1,
|
||||
},
|
||||
/*
|
||||
* H9HCNNNBPUMLHR-NLE - both logical channels. While the parts
|
||||
* are listed at 16Gb there are 2 ranks per channel so indicate the
|
||||
* density as 8Gb per rank.
|
||||
*/
|
||||
[4] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "H9HCNNNBPUMLHR",
|
||||
},
|
||||
/* H9HCNNN8KUMLHR-NLE - both logical channels */
|
||||
[5] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "H9HCNNN8KUMLHR",
|
||||
},
|
||||
};
|
||||
|
||||
static const struct lpddr4_cfg lp4cfg = {
|
||||
.skus = skus,
|
||||
.num_skus = ARRAY_SIZE(skus),
|
||||
.swizzle_config = &baseboard_lpddr4_swizzle,
|
||||
};
|
||||
|
||||
const struct lpddr4_cfg * __attribute__((weak)) variant_lpddr4_config(void)
|
||||
{
|
||||
return &lp4cfg;
|
||||
}
|
||||
|
||||
size_t __attribute__((weak)) variant_memory_sku(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2017 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <console/console.h>
|
||||
#include <nhlt.h>
|
||||
#include <soc/nhlt.h>
|
||||
|
||||
void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt)
|
||||
{
|
||||
/* 2 Channel DMIC array. */
|
||||
if (!nhlt_soc_add_dmic_array(nhlt, 2))
|
||||
printk(BIOS_ERR, "Added 2CH DMIC array.\n");
|
||||
|
||||
/* Dialog for Headset codec.
|
||||
* Headset codec is bi-directional but uses the same configuration
|
||||
* settings for render and capture endpoints.
|
||||
*/
|
||||
if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1))
|
||||
printk(BIOS_ERR, "Added Dialog_7219 codec.\n");
|
||||
|
||||
/* MAXIM Smart Amps for left and right speakers. */
|
||||
if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5))
|
||||
printk(BIOS_ERR, "Added Maxim_98357 codec.\n");
|
||||
}
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/acpi/dptf.asl>
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_EC_H
|
||||
#define MAINBOARD_EC_H
|
||||
|
||||
#include <baseboard/ec.h>
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#endif /* MAINBOARD_GPIO_H */
|
||||
Loading…
Reference in New Issue