mb/scaleway/tagada: Remove memory down option
The board does not have memory down, only 2 DDR4 Slots. Change-Id: I70eda83fbce7a707da170c7e555ed1a6dc6b1f4a Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Julien Viard de Galbert
Martin Roth
parent
3c5019dfd9
commit
d5a1928527
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@ -33,17 +33,4 @@ config MAINBOARD_VENDOR
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string
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default "Scaleway"
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config ENABLE_FSP_MEMORY_DOWN
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bool "Enable Memory Down"
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default n
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help
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Select this option to enable Memory Down function.
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config SPD_LOC
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depends on ENABLE_FSP_MEMORY_DOWN
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hex "SPD binary location in cbfs"
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default 0xfffdf000
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help
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Location of SPD binary for memory down function.
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endif # BOARD_SCALEWAY_TAGADA
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@ -14,8 +14,6 @@
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## GNU General Public License for more details.
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##
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subdirs-$(CONFIG_ENABLE_FSP_MEMORY_DOWN) += spd
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romstage-y += boardid.c
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romstage-y += hsio.c
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@ -16,70 +16,11 @@
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#include "harcuvar_boardid.h"
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#include "gpio.h"
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#include "spd/spd.h"
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#include <console/console.h>
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#include <fsp/api.h>
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#include <fsp/soc_binding.h>
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#include <string.h>
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#if IS_ENABLED(CONFIG_ENABLE_FSP_MEMORY_DOWN)
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/*
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* Define platform specific Memory Down Configure structure.
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*
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* If CONFIG_ENABLE_FSP_MEMORY_DOWN is enabled, the MEMORY_DOWN_CONFIG
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* structure should be customized to match the design.
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*
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* .SlotState indicates the memory down state of the specific channel/DIMM.
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*
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* SlotState options:
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*
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* STATE_MEMORY_DOWN: Memory down.
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* STATE_MEMORY_SLOT: Physical memory slot.
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*
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* .SpdDataLen should always be MAX_SPD_BYTES/512.
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*
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* .SpdDataPtr is pointing to the SPD data structure when memory modules
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* are memory down.
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*
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* SpdDataPtr options:
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*
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* Non-NULL: Pointing to SPD data structure.
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* NULL: Physical memory slot, no SPD data used.
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*
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* DIMM Mapping of SlotState & SpdDataPtr:
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*
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* {{CH0DIMM0, CH0DIMM1}, {CH1DIMM0, CH1DIMM1}}
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*
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* Sample: Channel 0 is memory down and channel 1 is physical slot.
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*
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* const MEMORY_DOWN_CONFIG mMemoryDownConfig = {
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* .SlotState = {
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* {STATE_MEMORY_DOWN, STATE_MEMORY_DOWN},
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* {STATE_MEMORY_SLOT, STATE_MEMORY_SLOT}
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* },
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* .SpdDataLen = MAX_SPD_BYTES,
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* .SpdDataPtr = {
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* {(void *)CONFIG_SPD_LOC, (void *)CONFIG_SPD_LOC},
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* {(void *)NULL, (void *)NULL}
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* }
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* }
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*/
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const MEMORY_DOWN_CONFIG mMemoryDownConfig = {
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.SlotState = {
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{STATE_MEMORY_SLOT, STATE_MEMORY_SLOT},
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{STATE_MEMORY_SLOT, STATE_MEMORY_SLOT}
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},
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.SpdDataLen = MAX_SPD_BYTES,
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.SpdDataPtr = {
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{(void *)NULL, (void *)NULL},
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{(void *)NULL, (void *)NULL}
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}
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};
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#endif /* CONFIG_ENABLE_FSP_MEMORY_DOWN */
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void mainboard_config_gpios(void);
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void mainboard_memory_init_params(FSPM_UPD *mupd);
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@ -118,27 +59,10 @@ void mainboard_config_gpios(void)
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void mainboard_memory_init_params(FSPM_UPD *mupd)
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{
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#if IS_ENABLED(CONFIG_ENABLE_FSP_MEMORY_DOWN)
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uint8_t *spd_data_ptr = NULL;
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mupd->FspmConfig.PcdFspDebugPrintErrorLevel = 3; // Verbose
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/* Get SPD data pointer */
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spd_data_ptr = mainboard_find_spd_data();
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if (spd_data_ptr != NULL) {
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printk(BIOS_DEBUG, "Memory Down function is enabled!\n");
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/* Enable Memory Down function, set Memory
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* Down Configure structure pointer.
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*/
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mupd->FspmConfig.PcdMemoryDown = 1;
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mupd->FspmConfig.PcdMemoryDownConfigPtr =
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(uint32_t)&mMemoryDownConfig;
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} else {
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printk(BIOS_DEBUG, "Memory Down function is disabled!\n");
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/* Disable Memory Down function */
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mupd->FspmConfig.PcdMemoryDown = 0;
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mupd->FspmConfig.PcdMemoryDownConfigPtr = 0;
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}
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#endif /* CONFIG_ENABLE_FSP_MEMORY_DOWN */
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// Enable Rmt and Fast Boot by default, RMT will be run only on first
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// boot or when dimms change
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mupd->FspmConfig.PcdMrcRmtSupport = 1;
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mupd->FspmConfig.PcdFastBoot = 1;
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}
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@ -1,38 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 Google Inc.
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## Copyright (C) 2015 - 2017 Intel Corporation.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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romstage-y += spd.c
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SPD_BIN = $(obj)/spd.bin
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# Order matters for SPD sources. The following indices
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# define the SPD data to use.
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SPD_SOURCES = micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2
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SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
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# Include spd rom data
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$(SPD_BIN): $(SPD_DEPS)
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for f in $+; \
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do for c in $$(cat $$f | grep -v ^#); \
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do echo -e -n "\\x$$c"; \
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done; \
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done > $@
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cbfs-files-y += spd.bin
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spd.bin-file := $(SPD_BIN)
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spd.bin-position := $(CONFIG_SPD_LOC)
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spd.bin-type := spd
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@ -1,513 +0,0 @@
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#DDR4_4GB_RDIMM_Micron_MTA9ASF51272PZ-2G1A2.txt
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00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
|
|
@ -1,58 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015 - 2017 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <arch/byteorder.h>
|
||||
#include <cbfs.h>
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "spd.h"
|
||||
|
||||
/* Get SPD data for on-board memory */
|
||||
uint8_t *mainboard_find_spd_data()
|
||||
{
|
||||
uint8_t *spd_data;
|
||||
int spd_index;
|
||||
size_t spd_file_len;
|
||||
char *spd_file;
|
||||
|
||||
spd_index = 0;
|
||||
|
||||
spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
|
||||
&spd_file_len);
|
||||
if (!spd_file)
|
||||
die("SPD data not found.");
|
||||
|
||||
if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
|
||||
printk(BIOS_ERR,
|
||||
"SPD index override to 0 due to incorrect SPD index.\n");
|
||||
spd_index = 0;
|
||||
}
|
||||
|
||||
if (spd_file_len < SPD_LEN)
|
||||
die("Missing SPD data.");
|
||||
|
||||
/* Assume same memory in both channels */
|
||||
spd_index *= SPD_LEN;
|
||||
spd_data = (uint8_t *)(spd_file + spd_index);
|
||||
|
||||
/* Make sure a valid SPD was found */
|
||||
if (spd_data[0] == 0)
|
||||
die("Invalid SPD data.");
|
||||
|
||||
return spd_data;
|
||||
}
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015 - 2017 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_SPD_H
|
||||
#define MAINBOARD_SPD_H
|
||||
|
||||
#define SPD_LEN 512
|
||||
|
||||
#define SPD_DRAM_TYPE 2
|
||||
#define SPD_DRAM_DDR3 0x0b
|
||||
#define SPD_DRAM_LPDDR3 0xf1
|
||||
#define SPD_DENSITY_BANKS 4
|
||||
#define SPD_ADDRESSING 5
|
||||
#define SPD_ORGANIZATION 7
|
||||
#define SPD_BUS_DEV_WIDTH 8
|
||||
#define SPD_PART_OFF 128
|
||||
#define SPD_PART_LEN 18
|
||||
|
||||
uint8_t *mainboard_find_spd_data(void);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue