mb/scaleway/tagada: Remove memory down option

The board does not have memory down, only 2 DDR4 Slots.

Change-Id: I70eda83fbce7a707da170c7e555ed1a6dc6b1f4a
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/scaleway/tagada/Kconfig

@@ -33,17 +33,4 @@ config MAINBOARD_VENDOR
 	string
 	default "Scaleway"
 
-config ENABLE_FSP_MEMORY_DOWN
-	bool "Enable Memory Down"
-	default n
-	help
-	  Select this option to enable Memory Down function.
-
-config SPD_LOC
-	depends on ENABLE_FSP_MEMORY_DOWN
-	hex "SPD binary location in cbfs"
-	default 0xfffdf000
-	help
-	  Location of SPD binary for memory down function.
-
 endif # BOARD_SCALEWAY_TAGADA

src/mainboard/scaleway/tagada/Makefile.inc

@@ -14,8 +14,6 @@
 ## GNU General Public License for more details.
 ##
 
-subdirs-$(CONFIG_ENABLE_FSP_MEMORY_DOWN) += spd
-
 romstage-y += boardid.c
 romstage-y += hsio.c
 

src/mainboard/scaleway/tagada/romstage.c

@@ -16,70 +16,11 @@
 
 #include "harcuvar_boardid.h"
 #include "gpio.h"
-#include "spd/spd.h"
 #include <console/console.h>
 #include <fsp/api.h>
 #include <fsp/soc_binding.h>
 #include <string.h>
 
-#if IS_ENABLED(CONFIG_ENABLE_FSP_MEMORY_DOWN)
-
-/*
- * Define platform specific Memory Down Configure structure.
- *
- * If CONFIG_ENABLE_FSP_MEMORY_DOWN is enabled, the MEMORY_DOWN_CONFIG
- * structure should be customized to match the design.
- *
- * .SlotState indicates the memory down state of the specific channel/DIMM.
- *
- * SlotState options:
- *
- *     STATE_MEMORY_DOWN: Memory down.
- *     STATE_MEMORY_SLOT: Physical memory slot.
- *
- * .SpdDataLen should always be MAX_SPD_BYTES/512.
- *
- * .SpdDataPtr is pointing to the SPD data structure when memory modules
- *             are memory down.
- *
- * SpdDataPtr options:
- *
- *     Non-NULL: Pointing to SPD data structure.
- *     NULL: Physical memory slot, no SPD data used.
- *
- * DIMM Mapping of SlotState & SpdDataPtr:
- *
- *     {{CH0DIMM0, CH0DIMM1}, {CH1DIMM0, CH1DIMM1}}
- *
- * Sample: Channel 0 is memory down and channel 1 is physical slot.
- *
- *	const MEMORY_DOWN_CONFIG mMemoryDownConfig = {
- *		.SlotState = {
- *			{STATE_MEMORY_DOWN, STATE_MEMORY_DOWN},
- *			{STATE_MEMORY_SLOT, STATE_MEMORY_SLOT}
- *		},
- *		.SpdDataLen = MAX_SPD_BYTES,
- *		.SpdDataPtr = {
- *			{(void *)CONFIG_SPD_LOC, (void *)CONFIG_SPD_LOC},
- *			{(void *)NULL, (void *)NULL}
- *		}
- *	}
- */
-
-const MEMORY_DOWN_CONFIG mMemoryDownConfig = {
-	.SlotState = {
-		{STATE_MEMORY_SLOT, STATE_MEMORY_SLOT},
-		{STATE_MEMORY_SLOT, STATE_MEMORY_SLOT}
-	},
-	.SpdDataLen = MAX_SPD_BYTES,
-	.SpdDataPtr = {
-		{(void *)NULL, (void *)NULL},
-		{(void *)NULL, (void *)NULL}
-	}
-};
-
-#endif /* CONFIG_ENABLE_FSP_MEMORY_DOWN */
-
 void mainboard_config_gpios(void);
 void mainboard_memory_init_params(FSPM_UPD *mupd);
 
@@ -118,27 +59,10 @@ void mainboard_config_gpios(void)
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
-#if IS_ENABLED(CONFIG_ENABLE_FSP_MEMORY_DOWN)
+	mupd->FspmConfig.PcdFspDebugPrintErrorLevel = 3; // Verbose
-	uint8_t *spd_data_ptr = NULL;
 
-	/* Get SPD data pointer */
+	// Enable Rmt and Fast Boot by default, RMT will be run only on first
-	spd_data_ptr = mainboard_find_spd_data();
+	// boot or when dimms change
-
+	mupd->FspmConfig.PcdMrcRmtSupport = 1;
-	if (spd_data_ptr != NULL) {
+	mupd->FspmConfig.PcdFastBoot = 1;
-		printk(BIOS_DEBUG, "Memory Down function is enabled!\n");
-
-		/* Enable Memory Down function, set Memory
-		 * Down Configure structure pointer.
-		 */
-		mupd->FspmConfig.PcdMemoryDown = 1;
-		mupd->FspmConfig.PcdMemoryDownConfigPtr =
-			(uint32_t)&mMemoryDownConfig;
-	} else {
-		printk(BIOS_DEBUG, "Memory Down function is disabled!\n");
-
-		/* Disable Memory Down function */
-		mupd->FspmConfig.PcdMemoryDown = 0;
-		mupd->FspmConfig.PcdMemoryDownConfigPtr = 0;
-	}
-#endif /* CONFIG_ENABLE_FSP_MEMORY_DOWN */
 }

src/mainboard/scaleway/tagada/spd/Makefile.inc

@@ -1,38 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 Google Inc.
-## Copyright (C) 2015 - 2017 Intel Corporation.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-romstage-y += spd.c
-
-SPD_BIN = $(obj)/spd.bin
-
-# Order matters for SPD sources. The following indices
-# define the SPD data to use.
-SPD_SOURCES = micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2
-
-SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-
-# Include spd rom data
-$(SPD_BIN): $(SPD_DEPS)
-	for f in $+; \
-	  do for c in $$(cat $$f | grep -v ^#); \
-	    do echo -e -n "\\x$$c"; \
-	  done; \
-	done > $@
-
-cbfs-files-y += spd.bin
-spd.bin-file := $(SPD_BIN)
-spd.bin-position := $(CONFIG_SPD_LOC)
-spd.bin-type := spd

src/mainboard/scaleway/tagada/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex

@@ -1,513 +0,0 @@
-#DDR4_4GB_RDIMM_Micron_MTA9ASF51272PZ-2G1A2.txt
-23
-10
-0C
-01
-84
-19
-00
-05
-00
-00
-00
-03
-01
-0B
-80
-00
-00
-00
-08
-0C
-F4
-1B
-00
-00
-6C
-6C
-6C
-11
-08
-74
-20
-08
-00
-05
-70
-03
-00
-A8
-1E
-2B
-2B
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-0E
-2E
-16
-36
-16
-36
-16
-36
-0E
-2E
-23
-04
-2B
-0C
-2B
-0C
-23
-04
-00
-00
-00
-00
-00
-00
-00
-00
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-EC
-B5
-CE
-00
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-00
-00
-C2
-64
-2B
-11
-11
-03
-05
-00
-86
-32
-B1
-00
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src/mainboard/scaleway/tagada/spd/spd.c

@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 - 2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <arch/byteorder.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <string.h>
-
-#include "spd.h"
-
-/* Get SPD data for on-board memory */
-uint8_t *mainboard_find_spd_data()
-{
-	uint8_t *spd_data;
-	int spd_index;
-	size_t spd_file_len;
-	char *spd_file;
-
-	spd_index = 0;
-
-	spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
-					   &spd_file_len);
-	if (!spd_file)
-		die("SPD data not found.");
-
-	if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
-		printk(BIOS_ERR,
-		       "SPD index override to 0 due to incorrect SPD index.\n");
-		spd_index = 0;
-	}
-
-	if (spd_file_len < SPD_LEN)
-		die("Missing SPD data.");
-
-	/* Assume same memory in both channels */
-	spd_index *= SPD_LEN;
-	spd_data = (uint8_t *)(spd_file + spd_index);
-
-	/* Make sure a valid SPD was found */
-	if (spd_data[0] == 0)
-		die("Invalid SPD data.");
-
-	return spd_data;
-}

src/mainboard/scaleway/tagada/spd/spd.h

@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 - 2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef MAINBOARD_SPD_H
-#define MAINBOARD_SPD_H
-
-#define SPD_LEN 512
-
-#define SPD_DRAM_TYPE 2
-#define SPD_DRAM_DDR3 0x0b
-#define SPD_DRAM_LPDDR3 0xf1
-#define SPD_DENSITY_BANKS 4
-#define SPD_ADDRESSING 5
-#define SPD_ORGANIZATION 7
-#define SPD_BUS_DEV_WIDTH 8
-#define SPD_PART_OFF 128
-#define SPD_PART_LEN 18
-
-uint8_t *mainboard_find_spd_data(void);
-
-#endif