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drivers/intel/fsp2_0: Update to FSP draft 9 

Recent FSP draft slightly changed FSP_INFO_HEADER structure. This
change keeps FSP driver code in sync with header changes.

Change-Id: I3536f766a312b9eb73ab8940d91dc9b9dfa347f1
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14614
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Andrey Petrov 2016-05-04 17:30:16 -07:00 committed by Martin Roth
parent 851ef96f4e
commit d5a6eb44ca
2 changed files with 35 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/drivers/intel/fsp2_0/include/fsp/info_header.h
View File

@ -21,15 +21,17 @@
#define FSP_HDR_OFFSET 0x94
#define FSP_HDR_LEN 0x48
#define FSP_HDR_SIGNATURE "FSPH"
#define FSP_HDR_ATTRIB_FSPT (0b0001 << 28)
#define FSP_HDR_ATTRIB_FSPM (0b0010 << 28)
#define FSP_HDR_ATTRIB_FSPS (0b0011 << 28)
#define FSP_HDR_ATTRIB_FSPT 0b0001
#define FSP_HDR_ATTRIB_FSPM 0b0010
#define FSP_HDR_ATTRIB_FSPS 0b0011
struct fsp_header {
uint32_t fsp_revision;
size_t image_size;
uintptr_t image_base;
uint32_t image_attribute;
uint16_t image_attribute;
uint8_t spec_version;
uint16_t component_attribute;
size_t cfg_region_offset;
size_t cfg_region_size;
size_t notify_phase_entry_offset;

34
src/drivers/intel/fsp2_0/util.c
View File

@ -42,13 +42,15 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob)
if (!looks_like_fsp_header(raw_hdr))
return CB_ERR;
hdr->spec_version = read8(raw_hdr + 10);
hdr->revision = read8(raw_hdr + 11);
hdr->fsp_revision = read32(raw_hdr + 12);
memcpy(hdr->image_id, raw_hdr + 16, ARRAY_SIZE(hdr->image_id));
hdr->image_id[ARRAY_SIZE(hdr->image_id) - 1] = '\0';
hdr->image_size = read32(raw_hdr + 24);
hdr->image_base = read32(raw_hdr + 28);
hdr->image_attribute = read32(raw_hdr + 32);
hdr->image_attribute = read16(raw_hdr + 32);
hdr->component_attribute = read16(raw_hdr + 34);
hdr->cfg_region_offset = read32(raw_hdr + 36);
hdr->cfg_region_size = read32(raw_hdr + 40);
hdr->notify_phase_entry_offset = read32(raw_hdr + 56);
@ -60,17 +62,39 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob)
void fsp_print_header_info(const struct fsp_header *hdr)
{
printk(BIOS_DEBUG, "Revision %u, image ID: %s, base 0x%lx + 0x%zx\n",
hdr->revision, hdr->image_id, hdr->image_base, hdr->image_size);
union {
uint32_t val;
struct {
uint8_t bld_num;
uint8_t revision;
uint8_t minor;
uint8_t major;
} rev;
} revision;
revision.val = hdr->fsp_revision;
printk(BIOS_DEBUG, "Spec version: v%u.%u\n", (hdr->spec_version >> 4 ),
hdr->spec_version & 0xf);
printk(BIOS_DEBUG, "Revision: %u.%u.%u, Build Number %u\n",
revision.rev.major,
revision.rev.minor,
revision.rev.revision,
revision.rev.bld_num);
printk(BIOS_DEBUG, "Type: %s/%s\n",
(hdr->component_attribute & 1 ) ? "release" : "debug",
(hdr->component_attribute & 2 ) ? "test" : "official");
printk(BIOS_DEBUG, "image ID: %s, base 0x%lx + 0x%zx\n",
hdr->image_id, hdr->image_base, hdr->image_size);
printk(BIOS_DEBUG, "\tConfig region 0x%zx + 0x%zx\n",
hdr->cfg_region_offset, hdr->cfg_region_size);
if (hdr->image_attribute & FSP_HDR_ATTRIB_FSPM) {
if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) {
printk(BIOS_DEBUG, "\tMemory init offset 0x%zx\n",
hdr->memory_init_entry_offset);
}
if (hdr->image_attribute & FSP_HDR_ATTRIB_FSPS) {
if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) {
printk(BIOS_DEBUG, "\tSilicon init offset 0x%zx\n",
hdr->silicon_init_entry_offset);
printk(BIOS_DEBUG, "\tNotify phase offset 0x%zx\n",