From d5a8155f1b90531201ae578e019182823614bcea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Feh=C3=A9r=20Roland=20=C3=81d=C3=A1m?= Date: Wed, 17 Oct 2018 18:41:49 +0200 Subject: [PATCH] util/inteltool: Fix LynxPoint (non-LP) GPIO register map MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The GPIO register dumper code for the LynxPoint family PCH chips (Intel 8 Series and C220 Series) was incorrectly using a shortened version of the LynxPoint-LP GPIO register map. Switched to the correct register map for the affected chipsets. Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f Signed-off-by: Fehér Roland Ádám Reviewed-on: https://review.coreboot.org/29167 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- util/inteltool/gpio.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index c38051c911..b4225a7e0e 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -869,9 +869,8 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; - gpio_registers = lynxpoint_lp_gpio_registers; - /* Shares register locations but has less of them */ - size = 29; + gpio_registers = pch_gpio_registers; + size = ARRAY_SIZE(pch_gpio_registers); break; case PCI_DEVICE_ID_INTEL_3400: case PCI_DEVICE_ID_INTEL_3420: