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mb/google/brya0: Update the FIVR configurations 

This patch sets the disable the external voltage rails since brya
board doesn't have V1p05 and Vnn bypass rails implemented.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
V Sowmya 2021-06-21 09:50:47 +05:30 committed by Felix Held
parent 590eb2bb9c
commit d5ab163086
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/google/brya/variants/brya0/overridetree.cb
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@ -36,6 +36,12 @@ chip soc/intel/alderlake
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
# FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn
# bypass rails implemented.
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
}"
device domain 0 on
device ref dtt on
chip drivers/intel/dptf