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soc/amd/common/acpi/cppc: add nominal and minimum frequencies 

Now that we have functionality to get the minimal and nominal
frequencies, the corresponding fields in the CPPC config can now be
populated. If the HOB isn't present and/or the frequency values
could not be obtained, CPPC_UNSUPPORTED is still used; otherwise the
HOB-provided frequency in MHz is used for those two fields.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: Id3257690a3388d44ceceb7ac4f1db3d49e195caa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66551
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2022-08-08 22:57:31 +02:00
parent 75547dbc53
commit d5ab24cd48
2 changed files with 11 additions and 2 deletions
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1
src/soc/amd/cezanne/Kconfig
View File

@ -68,6 +68,7 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UART
select SOC_AMD_COMMON_BLOCK_UCODE select SOC_AMD_COMMON_BLOCK_UCODE
select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_DMI_TABLES
select SOC_AMD_COMMON_FSP_PCI select SOC_AMD_COMMON_FSP_PCI
select SSE2 select SSE2

12
src/soc/amd/common/block/acpi/cppc.c
View File

@ -5,6 +5,7 @@
#include <amdblocks/cppc.h> #include <amdblocks/cppc.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <soc/msr.h> #include <soc/msr.h>
#include <types.h>
/* /*
* version 2 is expected to be the typical use case. * version 2 is expected to be the typical use case.
@ -13,6 +14,9 @@
*/ */
static void cpu_init_cppc_config(struct cppc_config *config, u32 version) static void cpu_init_cppc_config(struct cppc_config *config, u32 version)
{ {
uint32_t lowest_freq_mhz;
uint32_t nominal_freq_mhz;
config->version = version; config->version = version;
config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8); config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8);
@ -42,8 +46,12 @@ static void cpu_init_cppc_config(struct cppc_config *config, u32 version)
if (version < 3) if (version < 3)
return; return;
config->entries[CPPC_LOWEST_FREQ] = CPPC_UNSUPPORTED; config->entries[CPPC_LOWEST_FREQ] =
config->entries[CPPC_NOMINAL_FREQ] = CPPC_UNSUPPORTED; get_ccx_cppc_min_frequency(&lowest_freq_mhz) == CB_SUCCESS ?
CPPC_DWORD(lowest_freq_mhz) : CPPC_UNSUPPORTED;
config->entries[CPPC_NOMINAL_FREQ] =
get_ccx_cppc_nom_frequency(&nominal_freq_mhz) == CB_SUCCESS ?
CPPC_DWORD(nominal_freq_mhz) : CPPC_UNSUPPORTED;
} }
void generate_cppc_entries(unsigned int core_id) void generate_cppc_entries(unsigned int core_id)