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intel/amenia: Do not manually open up IO windows 

Do not use devicetree.cb to manually control hardware registers. This
interface will be removed in a subsequent commit and replaced with
runtime allocation that also does sanity checking.

Change-Id: I55561085ea467f19f52110b1a59f45fe290c7f09
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14582
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Alexandru Gagniuc 2016-03-31 13:23:52 -07:00 committed by Martin Roth
parent 7ec9b6c6ac
commit d5b7c55c46
1 changed files with 0 additions and 9 deletions
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9
src/mainboard/intel/amenia/devicetree.cb
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@ -7,15 +7,6 @@ chip soc/intel/apollolake
register "pcie_rp0_clkreq_pin" = "3" # wifi/bt register "pcie_rp0_clkreq_pin" = "3" # wifi/bt
register "pcie_rp2_clkreq_pin" = "0" # SSD register "pcie_rp2_clkreq_pin" = "0" # SSD
# EC host command range is in 0x800-0x9ff
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x00fc0901"
register "gen3_dec" = "0x0"
register "gen4_dec" = "0x0"
# EC also needs 0x200,0x204, 0x60/0x64, 0x62/0x66
register "lpc_dec" = "0xd00"
device domain 0 on device domain 0 on
device pci 00.0 on end # - Host Bridge device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF device pci 00.1 on end # - DPTF