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northbridge/amd/amdmct: Pack MCT and DCT info structs 

This allows safe access of romstage MCT values from ramstage

Change-Id: I229b19a64f7f148f970ec86dde7f4b6a62469064
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9158
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Timothy Pearson 2015-03-29 16:21:23 -05:00 committed by Patrick Georgi
parent 2e1f18336d
commit d5c82afa37
2 changed files with 4 additions and 4 deletions
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4
src/northbridge/amd/amdmct/mct/mct_d.h
View File

@ -260,7 +260,7 @@ struct MCTStatStruc {
of sub 4GB dram hole for HW remapping.*/ of sub 4GB dram hole for HW remapping.*/
u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/
u32 SysLimit; /* LIMIT[39:8] (system address)*/ u32 SysLimit; /* LIMIT[39:8] (system address)*/
}; } __attribute__((packed));
/*============================================================================= /*=============================================================================
Global MCT Configuration Status Word (GStatus) Global MCT Configuration Status Word (GStatus)
@ -512,7 +512,7 @@ struct DCTStatStruc { /* A per Node structure*/
u32 dev_map; u32 dev_map;
u32 dev_dct; u32 dev_dct;
u32 dev_nbmisc; u32 dev_nbmisc;
}; } __attribute__((packed));
/*=============================================================================== /*===============================================================================
Local Error Status Codes (DCTStatStruc.ErrCode) Local Error Status Codes (DCTStatStruc.ErrCode)

4
src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
View File

@ -287,7 +287,7 @@ struct MCTStatStruc {
of sub 4GB dram hole for HW remapping.*/ of sub 4GB dram hole for HW remapping.*/
u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/
u32 SysLimit; /* LIMIT[39:8] (system address)*/ u32 SysLimit; /* LIMIT[39:8] (system address)*/
}; } __attribute__((packed));
/*============================================================================= /*=============================================================================
Global MCT Configuration Status Word (GStatus) Global MCT Configuration Status Word (GStatus)
@ -575,7 +575,7 @@ struct DCTStatStruc { /* A per Node structure*/
struct _sMCTStruct s_C_MCTPtr; struct _sMCTStruct s_C_MCTPtr;
struct _sDCTStruct s_C_DCTPtr[2]; struct _sDCTStruct s_C_DCTPtr[2];
/* struct _sDCTStruct s_C_DCT1Ptr[8]; */ /* struct _sDCTStruct s_C_DCT1Ptr[8]; */
}; } __attribute__((packed));
/*=============================================================================== /*===============================================================================
Local Error Status Codes (DCTStatStruc.ErrCode) Local Error Status Codes (DCTStatStruc.ErrCode)