northbridge/amd/amdmct: Pack MCT and DCT info structs
This allows safe access of romstage MCT values from ramstage Change-Id: I229b19a64f7f148f970ec86dde7f4b6a62469064 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9158 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -260,7 +260,7 @@ struct MCTStatStruc {
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of sub 4GB dram hole for HW remapping.*/
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u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/
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u32 SysLimit; /* LIMIT[39:8] (system address)*/
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};
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} __attribute__((packed));
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/*=============================================================================
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Global MCT Configuration Status Word (GStatus)
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@ -512,7 +512,7 @@ struct DCTStatStruc { /* A per Node structure*/
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u32 dev_map;
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u32 dev_dct;
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u32 dev_nbmisc;
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};
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} __attribute__((packed));
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/*===============================================================================
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Local Error Status Codes (DCTStatStruc.ErrCode)
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@ -287,7 +287,7 @@ struct MCTStatStruc {
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of sub 4GB dram hole for HW remapping.*/
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u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/
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u32 SysLimit; /* LIMIT[39:8] (system address)*/
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};
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} __attribute__((packed));
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/*=============================================================================
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Global MCT Configuration Status Word (GStatus)
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@ -575,7 +575,7 @@ struct DCTStatStruc { /* A per Node structure*/
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struct _sMCTStruct s_C_MCTPtr;
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struct _sDCTStruct s_C_DCTPtr[2];
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/* struct _sDCTStruct s_C_DCT1Ptr[8]; */
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};
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} __attribute__((packed));
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/*===============================================================================
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Local Error Status Codes (DCTStatStruc.ErrCode)
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