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sb/intel/lynxpoint: Restore lost PCI_COMMAND_MASTER bits 

Commit 73ae076 "fixed" accesses to the PCI command register that were
not 16 bits, but also lost some bits to be written in the process.

Change-Id: I4eb62a0433a4563827a69c9e39c17ddd2eb8cd23
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Angel Pons 2020-05-31 01:03:59 +02:00
parent d49690bbe8
commit d5d4fbc072
3 changed files with 3 additions and 3 deletions
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2
src/southbridge/intel/lynxpoint/early_usb.c
View File

@ -25,7 +25,7 @@
static void enable_usb_bar_on_device(pci_devfn_t dev, u32 bar)
{
pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar);
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
}
void enable_usb_bar(void)

2
src/southbridge/intel/lynxpoint/me_9.x.c
View File

@ -735,7 +735,7 @@ static int intel_mei_setup(struct device *dev)
mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Clean up status for next message */
read_host_csr(&host);

2
src/southbridge/intel/lynxpoint/serialio.c
View File

@ -137,7 +137,7 @@ static void serialio_init(struct device *dev)
printk(BIOS_DEBUG, "Initializing Serial IO device\n");
/* Ensure memory and bus master are enabled */
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Find BAR0 and BAR1 */
bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);