soc/intel/cannonlake: Fix pcie clock number

Cannonlake PCH LP have total 6 pcie clocks and Cannonlake PCH H have
total 16 pcie clocks. It is different with pcie root port numbers.

BUG=CID 1381814
TEST=Build and boot up fine on sarien platform.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I909b5b584c596e6fe878ffe24d9cabc53c4576ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Zhao <john.zhao@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

src/soc/intel/cannonlake/Kconfig

@@ -183,6 +183,11 @@ config MAX_ROOT_PORTS
 	default 24 if SOC_INTEL_CANNONLAKE_PCH_H
 	default 16
 
+config MAX_PCIE_CLOCKS
+	int
+	default 16 if SOC_INTEL_CANNONLAKE_PCH_H
+	default 6
+
 config SMM_TSEG_SIZE
 	hex
 	default 0x800000

src/soc/intel/cannonlake/chip.h

@@ -168,10 +168,10 @@ struct soc_intel_cannonlake_config {
 	/* PCIe output clocks type to Pcie devices.
 	 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
 	 * 0xFF: not used */
-	uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS];
+	uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
 	/* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
 	 * clksrc. */
-	uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS];
+	uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
 	/* PCIe LTR(Latency Tolerance Reporting) mechanism */
 	uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
 	/* Enable/Disable HotPlug support for Root Port */