broadcom/cygnus: Initialize dram in romstage.
BUG=chrome-os-partner:36456 BRANCH=broadcom-firmware TEST=When enable configuration CYGNUS_SDRAM_TEST_DDR, print on console: sdram initialization is completed. test ddr start from 0x60000000 to 0x80000000 ... test ddr end: fail=0 Translation table is @ 02004000 Mapping address range [0x00000000:0x00000000) as uncached Change-Id: I88dc2f0c504e2a152133edd442c3d776dd73d37e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 376471751d6980f99bbe47faad193c79a05fa69f Original-Signed-off-by: Icarus Chau <ichau@broadcom.com> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/199775 Original-Commit-Queue: <ichau@broadcom.com> Original-Tested-by: <ichau@broadcom.com> Original-Reviewed-by: Scott Branden <sbranden@broadcom.com> Original-Change-Id: I47bc5d9ec147cc8bfbd893e8c0d7e5fc5e401771 Original-Reviewed-on: https://chromium-review.googlesource.com/256416 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9853 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Icarus Chau
Patrick Georgi
parent
1abb6002dd
commit
d5f551a82a
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@ -32,6 +32,8 @@ config SOC_BROADCOM_CYGNUS
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select HAVE_MONOTONIC_TIMER
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select HAVE_UART_MEMORY_MAPPED
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select HAVE_UART_SPECIAL
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select HAS_PRECBMEM_TIMESTAMP_REGION
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select RETURN_FROM_VERSTAGE
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if SOC_BROADCOM_CYGNUS
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@ -44,4 +46,19 @@ config CONSOLE_SERIAL_UART_ADDRESS
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depends on DRIVERS_UART
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default 0x18023000
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config CYGNUS_DDR800
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bool "DDR Speed at 800MHz"
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default y
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config CYGNUS_SHMOO_REUSE_DDR_32BIT
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bool "Indicate if DDR width is 32-bit"
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default n
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config CYGNUS_SDRAM_TEST_DDR
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bool "Run a write-read test on DDR after initialization"
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default n
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config CYGNUS_PRINT_SHMOO_DEBUG
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bool "Print debug info for shmoo"
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default n
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endif
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@ -26,7 +26,6 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
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bootblock-$(CONFIG_DRIVERS_UART) += ns16550.c
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endif
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verstage-y += verstage.c
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verstage-y += i2c.c
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verstage-y += timer.c
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verstage-$(CONFIG_SPI_FLASH) += spi.c
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@ -39,6 +38,12 @@ romstage-y += romstage.c
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romstage-y += sdram.c
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romstage-$(CONFIG_SPI_FLASH) += spi.c
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romstage-$(CONFIG_DRIVERS_UART) += ns16550.c
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romstage-y += ddr_init.c
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romstage-y += ddr_init_table.c
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romstage-y += shmoo_and28.c
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romstage-y += phy_reg_access.c
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romstage-y += ydc_ddr_bist.c
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romstage-y += timer.c
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ramstage-y += cbmem.c
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ramstage-y += i2c.c
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,32 @@
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/*
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __SOC_BROADCOM_CYGNUS_CONFIG_H__
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#define __SOC_BROADCOM_CYGNUS_CONFIG_H__
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#include <stdint.h>
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#include <string.h>
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#include <soc/halapis/ddr_regs.h>
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/* DDR shmoo Parameters */
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#define SDI_INTERFACE_BITWIDTH 16
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#define SDI_NUM_COLUMNS 1024
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#define SDI_NUM_BANKS 8
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#ifdef DDR3_SIZE_512MB
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#define SDI_NUM_ROWS 32768
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#else
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#define SDI_NUM_ROWS 65536
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#endif
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#endif /* __SOC_BROADCOM_CYGNUS_CONFIG_H__ */
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@ -0,0 +1,44 @@
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/*
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __SOC_BROADCOM_CYGNUS_CYGNUS_TYPES_H__
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#define __SOC_BROADCOM_CYGNUS_CYGNUS_TYPES_H__
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#include <stdint.h>
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#include <types.h>
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#ifndef TRUE
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#define TRUE (1 == 1)
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#endif
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#ifndef FALSE
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#define FALSE (1 == 0)
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#endif
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#ifndef NULL
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#define NULL 0
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#endif
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/**********************************************************************
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* Basic types
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**********************************************************************/
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typedef uint8_t uint8;
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typedef int8_t int8;
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typedef uint16_t uint16;
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typedef int16_t int16;
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typedef int32_t int32;
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typedef uint32_t uint32;
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#endif
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@ -0,0 +1,160 @@
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/*
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __SOC_BROADCOM_CYGNUS_DDR_BIST_H__
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#define __SOC_BROADCOM_CYGNUS_DDR_BIST_H__
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#include <soc/config.h>
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#define SOC_E_NONE (0)
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#define SOC_E_FAIL (-1)
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#define SOC_E_INTERNAL (-2)
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#define SOC_E_TIMEOUT (-3)
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#define SOC_E_PARAM (-4)
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#define SOC_E_MEMORY (-5)
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#define SOC_E_UNAVAIL (-6)
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#define SOC_E_CONFIG (-7)
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#define SOC_DDR3_CLOCK_MHZ(unit) iproc_get_ddr3_clock_mhz(unit)
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#define DDR_SHMOO_PARAM_MEM_PTR (0x1b000000) /*size ~0x300 */
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#define DDR_SHMOO_VREFW_MEM_PTR (0x50000000) /* size ~0x30000 */
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#define SOC_DDR3_NUM_MEMORIES (1)
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/* Convenience Macros - Arad Memory Controller - Recheck when MemC files change */
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enum drc_reg_set {
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DRC_BIST_CONFIGr = 0,
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DRC_BIST_CONFIG2r,
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DRC_BIST_GENERAL_CONFIGURATIONSr,
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DRC_BIST_CONFIGURATIONSr,
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DRC_BIST_NUMBER_OF_ACTIONSr,
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DRC_BIST_START_ADDRESSr,
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DRC_BIST_END_ADDRESSr,
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DRC_BIST_SINGLE_BIT_MASKr,
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DRC_BIST_PATTERN_WORD_7r,
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DRC_BIST_PATTERN_WORD_6r,
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DRC_BIST_PATTERN_WORD_5r,
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DRC_BIST_PATTERN_WORD_4r,
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DRC_BIST_PATTERN_WORD_3r,
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DRC_BIST_PATTERN_WORD_2r,
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DRC_BIST_PATTERN_WORD_1r,
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DRC_BIST_PATTERN_WORD_0r,
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DRC_BIST_FULL_MASK_WORD_7r,
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DRC_BIST_FULL_MASK_WORD_6r,
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DRC_BIST_FULL_MASK_WORD_5r,
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DRC_BIST_FULL_MASK_WORD_4r,
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DRC_BIST_FULL_MASK_WORD_3r,
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DRC_BIST_FULL_MASK_WORD_2r,
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DRC_BIST_FULL_MASK_WORD_1r,
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DRC_BIST_FULL_MASK_WORD_0r,
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DRC_BIST_STATUSESr,
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DRC_BIST_FULL_MASK_ERROR_COUNTERr,
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DRC_BIST_SINGLE_BIT_MASK_ERROR_COUNTERr,
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DRC_BIST_ERROR_OCCURREDr,
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DRC_BIST_GLOBAL_ERROR_COUNTERr,
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DRC_BIST_LAST_ADDR_ERRr,
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DRC_BIST_LAST_DATA_ERR_WORD_7r,
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DRC_BIST_LAST_DATA_ERR_WORD_6r,
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DRC_BIST_LAST_DATA_ERR_WORD_5r,
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DRC_BIST_LAST_DATA_ERR_WORD_4r,
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DRC_BIST_LAST_DATA_ERR_WORD_3r,
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DRC_BIST_LAST_DATA_ERR_WORD_2r,
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DRC_BIST_LAST_DATA_ERR_WORD_1r,
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DRC_BIST_LAST_DATA_ERR_WORD_0r
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};
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#define DRCA DDR_BistConfig
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#define DRCB DDR_BistConfig
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#define DRCC DDR_BistConfig
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#define DRCD DDR_BistConfig
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#define DRCE DDR_BistConfig
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#define DRCF DDR_BistConfig
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#define DRCG DDR_BistConfig
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#define DRCH DDR_BistConfig
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#define DRCALL DDR_BistConfig
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#define DRCA_BIST_CONFIGURATIONSr_RESERVEDf_SHIFT 26
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#define DRCA_BIST_CONFIGURATIONSr_RESERVEDf_WIDTH 6
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#define DRCA_BIST_CONFIGURATIONSr_BIST_ENf_SHIFT 25
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#define DRCA_BIST_CONFIGURATIONSr_BIST_ENf_WIDTH 1
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#define DRCA_BIST_CONFIGURATIONSr_DATA_ADDR_MODEf_SHIFT 24
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#define DRCA_BIST_CONFIGURATIONSr_DATA_ADDR_MODEf_WIDTH 1
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#define DRCA_BIST_CONFIGURATIONSr_DATA_SHIFT_MODEf_SHIFT 23
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#define DRCA_BIST_CONFIGURATIONSr_DATA_SHIFT_MODEf_WIDTH 1
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#define DRCA_BIST_CONFIGURATIONSr_ADDRESS_SHIFT_MODEf_SHIFT 22
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#define DRCA_BIST_CONFIGURATIONSr_ADDRESS_SHIFT_MODEf_WIDTH 1
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#define DRCA_BIST_CONFIGURATIONSr_CONS_ADDR_8_BANKSf_SHIFT 21
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#define DRCA_BIST_CONFIGURATIONSr_CONS_ADDR_8_BANKSf_WIDTH 1
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#define DRCA_BIST_CONFIGURATIONSr_CONS_ADDR_4_BANKSf_SHIFT 20
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#define DRCA_BIST_CONFIGURATIONSr_CONS_ADDR_4_BANKSf_WIDTH 1
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#define DRCA_BIST_CONFIGURATIONSr_IND_WR_RD_ADDR_MODEf_SHIFT 19
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#define DRCA_BIST_CONFIGURATIONSr_IND_WR_RD_ADDR_MODEf_WIDTH 1
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#define DRCA_BIST_CONFIGURATIONSr_PRBS_MODEf_SHIFT 18
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#define DRCA_BIST_CONFIGURATIONSr_PRBS_MODEf_WIDTH 1
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#define DRCA_BIST_CONFIGURATIONSr_TWO_ADDR_MODEf_SHIFT 17
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#define DRCA_BIST_CONFIGURATIONSr_TWO_ADDR_MODEf_WIDTH 1
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#define DRCA_BIST_CONFIGURATIONSr_PATTERN_BIT_MODEf_SHIFT 16
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#define DRCA_BIST_CONFIGURATIONSr_PATTERN_BIT_MODEf_WIDTH 1
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#define DRCA_BIST_CONFIGURATIONSr_READ_WEIGHTf_SHIFT 8
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#define DRCA_BIST_CONFIGURATIONSr_READ_WEIGHTf_WIDTH 8
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#define DRCA_BIST_CONFIGURATIONSr_WRITE_WEIGHTf_SHIFT 0
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#define DRCA_BIST_CONFIGURATIONSr_WRITE_WEIGHTf_WIDTH 8
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#define DRCA_BIST_NUMBER_OF_ACTIONSr_BIST_NUM_ACTIONSf_SHIFT 0
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#define DRCA_BIST_NUMBER_OF_ACTIONSr_BIST_NUM_ACTIONSf_WIDTH 32
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#define DRCA_BIST_START_ADDRESSr_BIST_START_ADDRESSf_SHIFT 0
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#define DRCA_BIST_START_ADDRESSr_BIST_START_ADDRESSf_WIDTH 26
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#define DRCA_BIST_START_ADDRESSr_RESERVED_SHIFT 26
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#define DRCA_BIST_START_ADDRESSr_RESERVED_WIDTH 6
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#define DRCA_BIST_END_ADDRESSr_BIST_END_ADDRESSf_SHIFT 0
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#define DRCA_BIST_END_ADDRESSr_BIST_END_ADDRESSf_WIDTH 26
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#define DRCA_BIST_END_ADDRESSr_RESERVED_SHIFT 26
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#define DRCA_BIST_END_ADDRESSr_RESERVED_WIDTH 6
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#define DRCA_BIST_STATUSESr_RESERVED_SHIFT 4
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#define DRCA_BIST_STATUSESr_RESERVED_WIDTH 28
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#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_RADDRf_SHIFT 3
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#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_RADDRf_WIDTH 1
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#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_CMDf_SHIFT 2
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#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_CMDf_WIDTH 1
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#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_WDATAf_SHIFT 1
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#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_WDATAf_WIDTH 1
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#define DRCA_BIST_STATUSESr_BIST_FINISHEDf_SHIFT 0
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#define DRCA_BIST_STATUSESr_BIST_FINISHEDf_WIDTH 1
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#define DRCA_BIST_ERROR_OCCURREDr_ERR_OCCURREDf_SHIFT 0
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#define DRCA_BIST_ERROR_OCCURREDr_ERR_OCCURREDf_WIDTH 32
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#define soc_reg_field_set(unit, r, m, f, data) \
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(*(m) = ((*(m) & ~(((1 << r##_##f##_WIDTH) - 1) << r##_##f##_SHIFT)) | ((data & ((1 << r##_##f##_WIDTH) - 1)) << r##_##f##_SHIFT)))
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#define soc_reg_field_get(unit, r, m, f) \
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((m >> r##_##f##_SHIFT) & ((1 << r##_##f##_WIDTH) - 1))
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#define DRC_REG_READ(unit, channel, reg, rvp) \
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soc_reg32_get((volatile uint32*)(channel + 4 * reg), rvp)
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#define DRC_REG_WRITE(unit, channel, reg, rv) \
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soc_reg32_set((volatile uint32*)(channel + 4 * reg), rv)
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#endif /* #ifndef __SOC_BROADCOM_CYGNUS_DDR_BIST_H__*/
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/* End of File */
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File diff suppressed because it is too large
Load Diff
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@ -24,10 +24,6 @@
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SECTIONS
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{
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DRAM_START(0x00000000)
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RAMSTAGE(0x00200000, 128K)
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POSTRAM_CBFS_CACHE(0x01000000, 1M)
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SRAM_START(0x02000000)
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REGION(reserved_for_system_status, 0x02000000, 4K, 4)
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TTB(0x02004000, 16K) /* must be aligned to 16K */
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@ -36,11 +32,14 @@ SECTIONS
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BOOTBLOCK(0x0200A440, 18K)
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PRERAM_CBMEM_CONSOLE(0x0200F000, 4K)
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VBOOT2_WORK(0x02010000, 16K)
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VERSTAGE(0x02014000, 48K)
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ROMSTAGE(0x02020000, 48K)
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PRERAM_CBFS_CACHE(0x0202C000, 1K)
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CBFS_HEADER_OFFSET(0x0202C800)
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STACK(0x0202D000, 12K)
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OVERLAP_VERSTAGE_ROMSTAGE(0x02014000, 120K)
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PRERAM_CBFS_CACHE(0x02032000, 1K)
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CBFS_HEADER_OFFSET(0x02032800)
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STACK(0x02033000, 12K)
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REGION(reserved_for_secure_service_api, 0x0203F000, 4K, 4)
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SRAM_END(0x02040000)
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DRAM_START(0x60000000)
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RAMSTAGE(0x60000000, 128K)
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POSTRAM_CBFS_CACHE(0x60100000, 1M)
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}
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@ -0,0 +1,182 @@
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/*
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*/
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#ifndef __SOC_BROADCOM_CYGNUS_REG_UTILS__
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#define __SOC_BROADCOM_CYGNUS_REG_UTILS__
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/* ---- Include Files ---------------------------------------------------- */
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#include <stdint.h>
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/* ---- Public Constants and Types --------------------------------------- */
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#define __REG32(x) (*((volatile uint32_t *)(x)))
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#define __REG16(x) (*((volatile uint16_t *)(x)))
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#define __REG8(x) (*((volatile uint8_t *) (x)))
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/* ---- Public Variable Externs ------------------------------------------ */
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/* ---- Public Function Prototypes --------------------------------------- */
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/****************************************************************************/
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/*
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* 32-bit register access functions
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*/
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/****************************************************************************/
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extern uint32_t reg_debug;
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#define REG_DEBUG(val) (reg_debug = val)
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static inline void
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reg32_clear_bits(volatile uint32_t *reg, uint32_t value)
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{
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#ifdef DEBUG_REG
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if (reg_debug)
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printf("%s reg (0x%x): 0x%x 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg, (*reg & ~(value)));
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#endif
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*reg &= ~(value);
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}
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static inline void
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reg32_set_bits(volatile uint32_t *reg, uint32_t value)
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{
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#ifdef DEBUG_REG
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if (reg_debug)
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printf("%s reg (0x%x): 0x%x 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg, (*reg | value));
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#endif
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*reg |= value;
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}
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static inline void
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reg32_toggle_bits(volatile uint32_t *reg, uint32_t value)
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{
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#ifdef DEBUG_REG
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if (reg_debug)
|
||||
printf("%s reg (0x%x): 0x%x 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg, (*reg ^ value));
|
||||
#endif
|
||||
*reg ^= value;
|
||||
}
|
||||
|
||||
static inline void
|
||||
reg32_write_masked(volatile uint32_t *reg, uint32_t mask, uint32_t value)
|
||||
{
|
||||
#ifdef DEBUG_REG
|
||||
if (reg_debug)
|
||||
printf("%s reg (0x%x): 0x%x 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg, (*reg & (~mask)) | (value & mask));
|
||||
#endif
|
||||
*reg = (*reg & (~mask)) | (value & mask);
|
||||
}
|
||||
|
||||
static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
|
||||
{
|
||||
#ifdef DEBUG_REG
|
||||
if (reg_debug)
|
||||
printf("%s reg (0x%x, 0x%x)\n", __FUNCTION__, (uint32_t)reg, value);
|
||||
#endif
|
||||
*reg = value;
|
||||
}
|
||||
|
||||
static inline uint32_t
|
||||
reg32_read(volatile uint32_t *reg)
|
||||
{
|
||||
#ifdef DEBUG_REG
|
||||
if (reg_debug)
|
||||
printf("%s reg (0x%x): 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg);
|
||||
#endif
|
||||
return *reg;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/*
|
||||
* 16-bit register access functions
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
static inline void
|
||||
reg16_clear_bits(volatile uint16_t *reg, uint16_t value)
|
||||
{
|
||||
*reg &= ~(value);
|
||||
}
|
||||
|
||||
static inline void
|
||||
reg16_set_bits(volatile uint16_t *reg, uint16_t value)
|
||||
{
|
||||
*reg |= value;
|
||||
}
|
||||
|
||||
static inline void
|
||||
reg16_toggle_bits(volatile uint16_t *reg, uint16_t value)
|
||||
{
|
||||
*reg ^= value;
|
||||
}
|
||||
|
||||
static inline void
|
||||
reg16_write_masked(volatile uint16_t *reg, uint16_t mask, uint16_t value)
|
||||
{
|
||||
*reg = (*reg & (~mask)) | (value & mask);
|
||||
}
|
||||
|
||||
static inline void
|
||||
reg16_write(volatile uint16_t *reg, uint16_t value)
|
||||
{
|
||||
*reg = value;
|
||||
}
|
||||
|
||||
static inline uint16_t
|
||||
reg16_read(volatile uint16_t *reg)
|
||||
{
|
||||
return *reg;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/*
|
||||
* 8-bit register access functions
|
||||
*/
|
||||
/****************************************************************************/
|
||||
|
||||
static inline void
|
||||
reg8_clear_bits(volatile uint8_t *reg, uint8_t value)
|
||||
{
|
||||
*reg &= ~(value);
|
||||
}
|
||||
|
||||
static inline void
|
||||
reg8_set_bits(volatile uint8_t *reg, uint8_t value)
|
||||
{
|
||||
*reg |= value;
|
||||
}
|
||||
|
||||
static inline void
|
||||
reg8_toggle_bits(volatile uint8_t *reg, uint8_t value)
|
||||
{
|
||||
*reg ^= value;
|
||||
}
|
||||
|
||||
static inline void
|
||||
reg8_write_masked(volatile uint8_t *reg, uint8_t mask, uint8_t value)
|
||||
{
|
||||
*reg = (*reg & (~mask)) | (value & mask);
|
||||
}
|
||||
|
||||
static inline void
|
||||
reg8_write(volatile uint8_t *reg, uint8_t value)
|
||||
{
|
||||
*reg = value;
|
||||
}
|
||||
|
||||
static inline uint8_t
|
||||
reg8_read(volatile uint8_t *reg)
|
||||
{
|
||||
return *reg;
|
||||
}
|
||||
#endif /* __SOC_BROADCOM_CYGNUS_REG_UTILS__ */
|
||||
|
||||
|
|
@ -20,6 +20,7 @@
|
|||
#ifndef __SOC_BROADCOM_CYGNUS_SDRAM_H__
|
||||
#define __SOC_BROADCOM_CYGNUS_SDRAM_H__
|
||||
|
||||
void ddr_init2(void);
|
||||
void sdram_init(void);
|
||||
|
||||
#endif /* __SOC_BROADCOM_CYGNUS_SDRAM_H__ */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_BROADCOM_CYGNUS_PHY_REG_ACCESS_H__
|
||||
#define __SOC_BROADCOM_CYGNUS_PHY_REG_ACCESS_H__
|
||||
|
||||
#include <soc/cygnus_types.h>
|
||||
#define GLOBAL_REG_RBUS_START 0x0000000000000000LL
|
||||
|
||||
uint32 REGRD(uint32 address);
|
||||
uint32 REGWR(uint32 address, uint32 data);
|
||||
|
||||
#define DDR_PHY_REG_READ(_unit, _pc, flags, _reg_addr, _val) \
|
||||
(*(uint32 *)_val = REGRD((_pc) + (_reg_addr)))
|
||||
/* soc_ddr40_phy_reg_ci_read((_unit), (_pc), (_reg_addr), (_val)) */
|
||||
#define DDR_PHY_REG_WRITE(_unit, _pc, _flags, _reg_addr, _val) \
|
||||
REGWR((_pc) + (_reg_addr), (_val))
|
||||
/* soc_ddr40_phy_reg_ci_write((_unit), (_pc), (_reg_addr), (_val)) */
|
||||
#define DDR_PHY_REG_MODIFY(_unit, _pc, _flags, _reg_addr, _val, _mask) \
|
||||
REGWR((_pc) + (_reg_addr), (REGRD((_pc) + (_reg_addr)) & ~(_mask)) | ((_val) & (_mask)))
|
||||
/* soc_ddr40_phy_reg_ci_modify((_unit), (_pc), (_reg_addr), (_val), (_mask)) */
|
||||
#define DDR_PHY_GET_FIELD(m, c, r, f) \
|
||||
GET_FIELD(m, c, r, f)
|
||||
#define DDR_PHY_SET_FIELD(m, c, r, f, d) \
|
||||
SET_FIELD(m, c, r, f, d)
|
||||
#endif /* __SOC_BROADCOM_CYGNUS_PHY_REG_ACCESS_H__ */
|
||||
|
|
@ -0,0 +1,267 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_BROADCOM_CYGNUS_SHMOO_AND28_H__
|
||||
#define __SOC_BROADCOM_CYGNUS_SHMOO_AND28_H__
|
||||
|
||||
#include <delay.h>
|
||||
#include <soc/cygnus_types.h>
|
||||
|
||||
#undef printf
|
||||
#if IS_ENABLED(CONFIG_CYGNUS_PRINT_SHMOO_DEBUG)
|
||||
#include <console/console.h>
|
||||
#define printf(args...) printk(BIOS_INFO, args)
|
||||
#else
|
||||
#define printf(args...)
|
||||
#endif
|
||||
|
||||
#ifndef SOC_E_NONE
|
||||
#define SOC_E_NONE 0x0
|
||||
#endif
|
||||
#ifndef SOC_E_FAIL
|
||||
#define SOC_E_FAIL 0x1
|
||||
#endif
|
||||
#ifndef SOC_E_TIMEOUT
|
||||
#define SOC_E_TIMEOUT 0x2
|
||||
#endif
|
||||
#ifndef SOC_E_MEMORY
|
||||
#define SOC_E_MEMORY 0x4
|
||||
#endif
|
||||
#define SET_ADDR_VDL_FORCE(v) (0x10000 | ((v) & 0x011FF))
|
||||
#define SET_VREF_DAC_CONTROL(v) ((v) & 0xFFFFF)
|
||||
#define SET_WR_VDL_FORCE(v) (0x10000 | ((v) & 0x011FF))
|
||||
#define SET_WR_CHAN_DLY_CYC_FORCE(v) (0x10000 | ((v) & 0x000F7))
|
||||
#define SET_RD_VDL_FORCE(v) (0x10000 | ((v) & 0x010FF))
|
||||
#define SET_RD_EN_DLY_CYC_FORCE(v) (0x10000 | ((v) & 0x001FF))
|
||||
#define SET_RD_CONTROL(v) ((v) & 0x0001F)
|
||||
|
||||
#define SHMOO_AND28_PHY_TYPE_RSVP 0
|
||||
#define SHMOO_AND28_PHY_TYPE_E0 0xE0
|
||||
#define SHMOO_AND28_PHY_TYPE_E2 0xE2
|
||||
#define SHMOO_AND28_PHY_TYPE_F0 0xF0
|
||||
|
||||
#define SHMOO_AND28_CTL_TYPE_RSVP 0
|
||||
#define SHMOO_AND28_CTL_TYPE_RSVP_STR "t0"
|
||||
#define SHMOO_AND28_CTL_TYPE_1 1
|
||||
#define SHMOO_AND28_CTL_TYPE_1_STR "t1"
|
||||
|
||||
#define SHMOO_AND28_DRAM_TYPE_RSVP 0
|
||||
#define SHMOO_AND28_DRAM_TYPE_DDR3 3
|
||||
#define SHMOO_AND28_DRAM_TYPE_DDR3L 31
|
||||
#define SHMOO_AND28_DRAM_TYPE_DDR4 4
|
||||
#define SHMOO_AND28_DRAM_TYPE_GDDR5 5
|
||||
|
||||
#define SHMOO_AND28_PHY_REG_BASE_RSVP 0
|
||||
#define SHMOO_AND28_PHY_REG_BASE_CYGNUS 0x18011000
|
||||
#define SHMOO_AND28_PHY_REG_BASE_GREYHOUND 0x18011000
|
||||
|
||||
#define SHMOO_AND28_YDC_DDR_BIST_REG_BASE_RSVP 0
|
||||
#define SHMOO_AND28_YDC_DDR_BIST_REG_BASE_GREYHOUND 0x18010C00
|
||||
|
||||
#define SHMOO_AND28_CHIP_ID_RSVP 0
|
||||
#define SHMOO_AND28_CHIP_ID_CYGNUS 0xC
|
||||
#define SHMOO_AND28_CHIP_ID_GREYHOUND 0x6
|
||||
|
||||
#define SHMOO_AND28_CHIP_ID SHMOO_AND28_CHIP_ID_CYGNUS
|
||||
#define SHMOO_AND28_PHY_TYPE SHMOO_AND28_PHY_TYPE_E2
|
||||
#define SHMOO_AND28_PHY_REG_BASE SHMOO_AND28_PHY_REG_BASE_CYGNUS
|
||||
#define SHMOO_AND28_YDC_DDR_BIST_REG_BASE SHMOO_AND28_YDC_DDR_BIST_REG_BASE_CYGNUS
|
||||
#define SHMOO_AND28_CTL_TYPE SHMOO_AND28_CTL_TYPE_1
|
||||
#define SHMOO_AND28_DRAM_TYPE SHMOO_AND28_DRAM_TYPE_DDR3L
|
||||
#define SHMOO_AND28_PHY_BITWIDTH 16
|
||||
#define SHMOO_AND28_PHY_CONSTANT_CONFIG 0
|
||||
#define PHY_AND28_E2 SHMOO_AND28_PHY_TYPE
|
||||
|
||||
#define SHMOO_AND28_PHY_BITWIDTH_IS_32 (SHMOO_AND28_PHY_BITWIDTH >> 5)
|
||||
#define YDC_DDR_BIST_PHY_BITWIDTH_IS_32 SHMOO_AND28_PHY_BITWIDTH_IS_32
|
||||
#define YDC_DDR_BIST_REG_BASE SHMOO_AND28_YDC_DDR_BIST_REG_BASE
|
||||
|
||||
#define SHMOO_AND28_BIT 1
|
||||
#define SHMOO_AND28_BYTE (SHMOO_AND28_BIT << 3)
|
||||
#define SHMOO_AND28_HALFWORD (SHMOO_AND28_BYTE << 1)
|
||||
#define SHMOO_AND28_WORD (SHMOO_AND28_HALFWORD << 1)
|
||||
#define SHMOO_AND28_DOUBLEWORD (SHMOO_AND28_WORD << 1)
|
||||
#define SHMOO_AND28_QUADWORD (SHMOO_AND28_DOUBLEWORD << 1)
|
||||
|
||||
#define SHMOO_AND28_SHORT_SLEEP 1
|
||||
#define SHMOO_AND28_LONG_SLEEP 10
|
||||
#define SHMOO_AND28_DEEP_SLEEP 100
|
||||
#define SHMOO_AND28_HIBERNATION 1000
|
||||
#define SHMOO_AND28_STASIS 1000000
|
||||
|
||||
#define SHMOO_AND28_SHMOO_RSVP -1
|
||||
#define SHMOO_AND28_RD_EN 23
|
||||
#define SHMOO_AND28_RD_EXTENDED 50
|
||||
#define SHMOO_AND28_WR_EXTENDED 60
|
||||
#define SHMOO_AND28_ADDR_EXTENDED 71
|
||||
#define SHMOO_AND28_CTRL_EXTENDED 72
|
||||
#define SHMOO_AND28_DDR3_SEQUENCE_COUNT 5
|
||||
#define SHMOO_AND28_DDR3L_SEQUENCE_COUNT 5
|
||||
/* BEGIN: EXTRA */
|
||||
/* END: EXTRA */
|
||||
|
||||
#define SHMOO_AND28_QUICK_SHMOO_CTRL_EXTENDED 1
|
||||
|
||||
#define SHMOO_AND28_REPEAT 9
|
||||
#define SHMOO_AND28_REPEAT_HALF (SHMOO_COMBO28_REPEAT >> 1)
|
||||
|
||||
#define SHMOO_AND28_SEQUENTIAL 0
|
||||
#define SHMOO_AND28_SINGLE 1
|
||||
|
||||
#define SHMOO_AND28_ACTION_RSVP -1
|
||||
#define SHMOO_AND28_ACTION_RESTORE 0
|
||||
#define SHMOO_AND28_ACTION_RUN 1
|
||||
#define SHMOO_AND28_ACTION_SAVE 2
|
||||
#define SHMOO_AND28_ACTION_RUN_AND_SAVE 3
|
||||
|
||||
#define SHMOO_AND28_MAX_INTERFACES 8
|
||||
#define SHMOO_AND28_INTERFACE_RSVP -1
|
||||
#define SHMOO_AND28_BYTES_PER_INTERFACE 4
|
||||
|
||||
#define SHMOO_AND28_BIST_NOF_PATTERNS 8
|
||||
#define SHMOO_AND28_BIST_MPR_NOF_PATTERNS 4
|
||||
|
||||
#define SHMOO_AND28_MAX_VISIBLE_UI_COUNT 4
|
||||
#define SHMOO_AND28_MAX_EFFECTIVE_UI_COUNT 4
|
||||
#define SHMOO_AND28_LAST_EFFECTIVE_UI (SHMOO_AND28_MAX_EFFECTIVE_UI_COUNT - 1)
|
||||
#define SHMOO_AND28_MAX_VDL_LENGTH 256
|
||||
#define SHMOO_AND28_MAX_VREF_RANGE 64
|
||||
#define SHMOO_AND28_MAX_ZQ_CAL_RANGE 32
|
||||
|
||||
#define SHMOO_AND28_RESULT2D_X SHMOO_AND28_MAX_VDL_LENGTH
|
||||
#define SHMOO_AND28_RESULT2D_Y SHMOO_AND28_MAX_VREF_RANGE
|
||||
|
||||
#define SHMOO_AND28_STRING_LENGTH (SHMOO_AND28_RESULT2D_X + 1)
|
||||
#define SHMOO_AND28_ERROR_ARRAY_LENGTH 4
|
||||
|
||||
#define SHMOO_AND28_CALIB_CENTER_PASS 111
|
||||
#define SHMOO_AND28_CALIB_RISING_EDGE 011
|
||||
#define SHMOO_AND28_CALIB_FALLING_EDGE 100
|
||||
#define SHMOO_AND28_CALIB_PASS_START 001
|
||||
#define SHMOO_AND28_CALIB_FAIL_START 110
|
||||
#define SHMOO_AND28_CALIB_VDL_ZERO 000
|
||||
|
||||
#define SHMOO_AND28_VDL_TFIX 18
|
||||
|
||||
#define SHMOO_AND28_RD_DATA_DLY_INIT 7
|
||||
|
||||
#define SHMOO_AND28_RD_EN_CYC_INIT 1
|
||||
|
||||
#define SHMOO_AND28_RD_EN_VDL_INIT 0
|
||||
|
||||
#define SHMOO_AND28_RD_DQ_VDL_INIT 0
|
||||
#define SHMOO_AND28_RD_DQ_FAIL_CAP 5
|
||||
|
||||
#define SHMOO_AND28_RD_DQS_VDL_OFFSET SHMOO_AND28_RD_DQ_VDL_INIT
|
||||
|
||||
#define SHMOO_AND28_WR_CYC_INIT 0
|
||||
|
||||
#define SHMOO_AND28_PHY_NOF_AD 16
|
||||
#define SHMOO_AND28_PHY_NOF_BA 3
|
||||
#define SHMOO_AND28_PHY_NOF_AUX 3
|
||||
#define SHMOO_AND28_PHY_NOF_CS 2
|
||||
|
||||
typedef struct and28_shmoo_dram_info_s {
|
||||
uint32 ctl_type;
|
||||
uint32 dram_type;
|
||||
uint32 dram_bitmap;
|
||||
uint32 interface_bitwidth;
|
||||
int num_columns;
|
||||
int num_rows;
|
||||
int num_banks;
|
||||
int data_rate_mbps;
|
||||
int ref_clk_mhz;
|
||||
uint32 refi;
|
||||
uint32 command_parity_latency;
|
||||
int sim_system_mode;
|
||||
} and28_shmoo_dram_info_t;
|
||||
|
||||
typedef struct and28_shmoo_config_param_s {
|
||||
uint16 control_regs_ad[SHMOO_AND28_PHY_NOF_AD];
|
||||
uint16 control_regs_ba[SHMOO_AND28_PHY_NOF_BA];
|
||||
uint16 control_regs_aux[SHMOO_AND28_PHY_NOF_AUX];
|
||||
uint16 control_regs_cs[SHMOO_AND28_PHY_NOF_CS];
|
||||
uint16 control_regs_par;
|
||||
uint16 control_regs_ras_n;
|
||||
uint16 control_regs_cas_n;
|
||||
uint16 control_regs_cke;
|
||||
uint16 control_regs_rst_n;
|
||||
uint16 control_regs_odt;
|
||||
uint16 control_regs_we_n;
|
||||
uint32 control_regs_vref_dac_control;
|
||||
|
||||
uint16 wr_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE];
|
||||
uint16 wr_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE];
|
||||
uint16 wr_vdl_dq[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE];
|
||||
uint16 wr_vdl_dm[SHMOO_AND28_BYTES_PER_INTERFACE];
|
||||
uint16 wr_vdl_edc[SHMOO_AND28_BYTES_PER_INTERFACE];
|
||||
uint8 wr_chan_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE];
|
||||
|
||||
uint16 rd_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE];
|
||||
uint16 rd_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE];
|
||||
uint16 rd_vdl_dqp[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE];
|
||||
uint16 rd_vdl_dqn[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE];
|
||||
uint16 rd_vdl_dmp[SHMOO_AND28_BYTES_PER_INTERFACE];
|
||||
uint16 rd_vdl_dmn[SHMOO_AND28_BYTES_PER_INTERFACE];
|
||||
uint16 rd_en_vdl_cs[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_PHY_NOF_CS];
|
||||
uint16 rd_en_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE];
|
||||
uint8 rd_control[SHMOO_AND28_BYTES_PER_INTERFACE];
|
||||
} and28_shmoo_config_param_t;
|
||||
|
||||
typedef struct and28_vendor_info_s {
|
||||
uint32 dram_density;
|
||||
uint32 fifo_depth;
|
||||
uint32 revision_id;
|
||||
uint32 manufacture_id;
|
||||
} and28_vendor_info_t;
|
||||
|
||||
typedef struct and28_shmoo_container_s {
|
||||
uint32 sizeX;
|
||||
uint32 sizeY;
|
||||
uint32 yCapMin;
|
||||
uint32 yCapMax;
|
||||
uint32 yJump;
|
||||
uint32 calibMode;
|
||||
uint32 calibPos;
|
||||
uint32 calibStart;
|
||||
uint32 result2D[(SHMOO_AND28_RESULT2D_X)*(SHMOO_AND28_RESULT2D_Y)];
|
||||
uint32 resultData[SHMOO_AND28_WORD];
|
||||
uint32 shmooType;
|
||||
uint32 dramType;
|
||||
uint32 ctlType;
|
||||
uint32 trefi;
|
||||
uint32 step1000;
|
||||
uint32 size1000UI;
|
||||
uint32 endUI[SHMOO_AND28_MAX_VISIBLE_UI_COUNT];
|
||||
uint32 engageUIshift;
|
||||
uint32 wckInv;
|
||||
} and28_shmoo_container_t;
|
||||
|
||||
typedef struct and28_step_size_s {
|
||||
uint32 step1000;
|
||||
uint32 size1000UI;
|
||||
} and28_step_size_t;
|
||||
|
||||
typedef struct and28_ui_position_s {
|
||||
uint32 ui;
|
||||
uint32 position;
|
||||
} and28_ui_position_t;
|
||||
|
||||
typedef uint32 and28_shmoo_error_array_t[SHMOO_AND28_ERROR_ARRAY_LENGTH];
|
||||
|
||||
int soc_and28_shmoo_dram_info_set(int unit, and28_shmoo_dram_info_t *sdi);
|
||||
int soc_and28_shmoo_phy_init(int unit, int phy_ndx);
|
||||
int soc_and28_shmoo_ctl(int unit, int phy_ndx, int shmoo_type, int stat,
|
||||
int plot, int action, and28_shmoo_config_param_t *config_param);
|
||||
|
||||
#endif /* __SOC_BROADCOM_CYGNUS_SHMOO_AND28_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "soc/shmoo_and28/phy_reg_access.h"
|
||||
|
||||
uint32 REGRD (uint32 address) {
|
||||
|
||||
volatile unsigned long data;
|
||||
|
||||
data = (* (volatile uint32 *) ( ((uint32)GLOBAL_REG_RBUS_START) | (address)));
|
||||
//printf("REGRD %08X=%08X\n", address, data);
|
||||
return data;
|
||||
}
|
||||
|
||||
uint32 REGWR (uint32 address, uint32 data) {
|
||||
|
||||
((* (volatile uint32 *) ( ((uint32)GLOBAL_REG_RBUS_START) | (address))) = data);
|
||||
//printf("REGWR %08X=%08X\n", address, data);
|
||||
// return SOC_E_NONE;
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -17,9 +17,46 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#include <console/console.h>
|
||||
#include <symbols.h>
|
||||
#include <soc/sdram.h>
|
||||
|
||||
#define DRAM_TEST_LEN 0x8000000
|
||||
|
||||
static void test_ddr(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_CYGNUS_SDRAM_TEST_DDR)) {
|
||||
uint32_t *test_buffer = (uint32_t *) _dram;
|
||||
uint32_t len = DRAM_TEST_LEN;
|
||||
uint32_t i;
|
||||
uint32_t fail_count = 0;
|
||||
|
||||
printk(BIOS_INFO, "test ddr start from 0x%p to 0x%p\n", test_buffer,
|
||||
test_buffer + len);
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
*(test_buffer + i) = i;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
int val = *(test_buffer + i);
|
||||
|
||||
if ((i % 0x10000) == 0)
|
||||
printk(BIOS_INFO, "#");
|
||||
|
||||
if (i != val) {
|
||||
printk(BIOS_ERR, "\ntest_ddr: @ 0x%p: %d != %d\n",
|
||||
test_buffer + i, i, val);
|
||||
fail_count++;
|
||||
}
|
||||
}
|
||||
printk(BIOS_INFO, "\ntest ddr end: fail=%d\n", fail_count);
|
||||
}
|
||||
}
|
||||
|
||||
void sdram_init(void)
|
||||
{
|
||||
printk(BIOS_INFO, "sdram initialization is not implemented\n");
|
||||
printk(BIOS_INFO, "sdram initialization is in progress...\n");
|
||||
ddr_init2();
|
||||
printk(BIOS_INFO, "sdram initialization is completed.\n");
|
||||
|
||||
test_ddr();
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,170 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <soc/cygnus_types.h>
|
||||
#include <console/console.h>
|
||||
|
||||
#define SOC_IF_ERROR_RETURN(x) (x)
|
||||
#define sal_alloc(x,y) malloc(x)
|
||||
#define sal_memset(x,y,z) memset(x,y,z)
|
||||
#define sal_free(x) free(x)
|
||||
#define sal_usleep(x) udelay(x)
|
||||
|
||||
/* BEGIN: TEMPORARY */
|
||||
#ifndef BCM_AND28_SUPPORT
|
||||
#define BCM_AND28_SUPPORT
|
||||
#endif
|
||||
/* END: TEMPORARY */
|
||||
|
||||
#ifdef BCM_AND28_SUPPORT
|
||||
#include <soc/shmoo_and28/ydc_ddr_bist.h>
|
||||
#include <soc/shmoo_and28/phy_reg_access.h>
|
||||
#endif
|
||||
|
||||
/* BEGIN: HELPER FUNCTIONS */
|
||||
static uint32
|
||||
_get_random28(void)
|
||||
{
|
||||
static uint32 m_w = 6483; /* must not be zero */
|
||||
static uint32 m_z = 31245; /* must not be zero */
|
||||
|
||||
m_z = 36969 * (m_z & 65535) + (m_z >> 16);
|
||||
m_w = 18000 * (m_w & 65535) + (m_w >> 16);
|
||||
return (m_z << 16) + m_w; /* 32-bit result */
|
||||
}
|
||||
/* END: HELPER FUNCTIONS */
|
||||
|
||||
int
|
||||
soc_ydc_ddr_bist_config_set(int unit, int phy_ndx, ydc_ddr_bist_info_t *bist_info)
|
||||
{
|
||||
uint32 data;
|
||||
|
||||
READ_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, &data);
|
||||
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, WRITE_WEIGHT, (*bist_info).write_weight);
|
||||
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, READ_WEIGHT, (*bist_info).read_weight);
|
||||
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, PATTERN_BIT_MODE, 0);
|
||||
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, PRBS_MODE, (*bist_info).prbs_mode);
|
||||
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, CONS_ADDR_8_BANKS, 1);
|
||||
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, ADDRESS_SHIFT_MODE, 0);
|
||||
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, DATA_SHIFT_MODE, 0);
|
||||
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, DATA_ADDR_MODE, 0);
|
||||
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, IND_WR_RD_ADDR_MODE, 1);
|
||||
WRITE_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, data);
|
||||
|
||||
if(!((*bist_info).prbs_mode))
|
||||
{
|
||||
if((*bist_info).mpr_mode)
|
||||
{
|
||||
if(YDC_DDR_BIST_PHY_BITWITDH_IS_32)
|
||||
{
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_0r(0, YDC_DDR_BIST_REG_BASE, 0xFFFFFFFF);
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_1r(0, YDC_DDR_BIST_REG_BASE, 0x00000000);
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_2r(0, YDC_DDR_BIST_REG_BASE, 0xFFFFFFFF);
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_3r(0, YDC_DDR_BIST_REG_BASE, 0x00000000);
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_4r(0, YDC_DDR_BIST_REG_BASE, 0xFFFFFFFF);
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_5r(0, YDC_DDR_BIST_REG_BASE, 0x00000000);
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_6r(0, YDC_DDR_BIST_REG_BASE, 0xFFFFFFFF);
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_7r(0, YDC_DDR_BIST_REG_BASE, 0x00000000);
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_0r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_1r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_2r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_3r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_4r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_5r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_6r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_7r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_0r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_1r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_2r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_3r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_4r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_5r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_6r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
|
||||
WRITE_YDC_DDR_BIST_PATTERN_WORD_7r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
|
||||
}
|
||||
}
|
||||
|
||||
READ_YDC_DDR_BIST_NUMBER_OF_ACTIONSr(0, YDC_DDR_BIST_REG_BASE, &data);
|
||||
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, NUMBER_OF_ACTIONS, BIST_NUM_ACTIONS, (*bist_info).bist_num_actions);
|
||||
WRITE_YDC_DDR_BIST_NUMBER_OF_ACTIONSr(0, YDC_DDR_BIST_REG_BASE, data);
|
||||
|
||||
READ_YDC_DDR_BIST_START_ADDRESSr(0, YDC_DDR_BIST_REG_BASE, &data);
|
||||
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, START_ADDRESS, BIST_START_ADDRESS, (*bist_info).bist_start_address);
|
||||
WRITE_YDC_DDR_BIST_START_ADDRESSr(0, YDC_DDR_BIST_REG_BASE, data);
|
||||
|
||||
READ_YDC_DDR_BIST_END_ADDRESSr(0, YDC_DDR_BIST_REG_BASE, &data);
|
||||
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, END_ADDRESS, BIST_END_ADDRESS, (*bist_info).bist_end_address);
|
||||
WRITE_YDC_DDR_BIST_END_ADDRESSr(0, YDC_DDR_BIST_REG_BASE, data);
|
||||
|
||||
return SOC_E_NONE;
|
||||
}
|
||||
|
||||
int
|
||||
soc_ydc_ddr_bist_run(int unit, int phy_ndx, ydc_ddr_bist_err_cnt_t *error_count)
|
||||
{
|
||||
uint32 data;
|
||||
uint32 poll_count;
|
||||
|
||||
READ_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, &data);
|
||||
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, BIST_EN, 1);
|
||||
WRITE_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, data);
|
||||
|
||||
poll_count = 0;
|
||||
|
||||
while(TRUE)
|
||||
{
|
||||
READ_YDC_DDR_BIST_STATUSESr(0, YDC_DDR_BIST_REG_BASE, &data);
|
||||
|
||||
if(YDC_DDR_BIST_GET_FIELD(data, YDC_DDR_BIST, STATUSES, BIST_FINISHED))
|
||||
{
|
||||
READ_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, &data);
|
||||
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, BIST_EN, 0);
|
||||
WRITE_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, data);
|
||||
break;
|
||||
}
|
||||
|
||||
if(poll_count > YDC_DDR_BIST_POLL_COUNT_LIMIT)
|
||||
{
|
||||
READ_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, &data);
|
||||
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, BIST_EN, 0);
|
||||
WRITE_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, data);
|
||||
|
||||
printk(BIOS_ERR, "ERROR: YDC DDR BIST timeout!!!\n");
|
||||
return SOC_E_TIMEOUT;
|
||||
}
|
||||
|
||||
poll_count++;
|
||||
sal_usleep(YDC_DDR_BIST_POLL_INTERVAL_US);
|
||||
}
|
||||
|
||||
READ_YDC_DDR_BIST_ERROR_OCCURREDr(0, YDC_DDR_BIST_REG_BASE, &data);
|
||||
(*error_count).bist_err_occur = YDC_DDR_BIST_GET_FIELD(data, YDC_DDR_BIST, ERROR_OCCURRED, ERR_OCCURRED);
|
||||
|
||||
READ_YDC_DDR_BIST_FULL_MASK_ERROR_COUNTERr(0, YDC_DDR_BIST_REG_BASE, &data);
|
||||
(*error_count).bist_full_err_cnt = YDC_DDR_BIST_GET_FIELD(data, YDC_DDR_BIST, FULL_MASK_ERROR_COUNTER, FULL_ERR_CNT);
|
||||
|
||||
READ_YDC_DDR_BIST_SINGLE_BIT_MASK_ERROR_COUNTERr(0, YDC_DDR_BIST_REG_BASE, &data);
|
||||
(*error_count).bist_single_err_cnt = YDC_DDR_BIST_GET_FIELD(data, YDC_DDR_BIST, SINGLE_BIT_MASK_ERROR_COUNTER, SINGLE_ERR_CNT);
|
||||
|
||||
READ_YDC_DDR_BIST_GLOBAL_ERROR_COUNTERr(0, YDC_DDR_BIST_REG_BASE, &data);
|
||||
(*error_count).bist_global_err_cnt = YDC_DDR_BIST_GET_FIELD(data, YDC_DDR_BIST, GLOBAL_ERROR_COUNTER, GLOBAL_ERR_CNT);
|
||||
|
||||
return SOC_E_NONE;
|
||||
}
|
||||
Loading…
Reference in New Issue