soc/intel: Replace config_of_path() with config_of_soc()

The previously provided device path made no difference, all
integrated PCI devices point back to the same chip_info
structure.

Change reduces the exposure of various SA_DEVFN_xx and
PCH_DEVFN_xx from (ugly) soc/pci_devs.h.

Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2019-09-28 00:20:27 +03:00 committed by Patrick Georgi
parent d3d38c95b7
commit d5f645c6cd
46 changed files with 72 additions and 79 deletions

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@ -321,16 +321,9 @@ static inline DEVTREE_CONST void *config_of(const struct device *dev)
devtree_die(); devtree_die();
} }
static inline DEVTREE_CONST void *config_of_path(pci_devfn_t devfn) static inline DEVTREE_CONST void *config_of_soc(void)
{ {
const struct device *dev = pcidev_path_on_root(devfn); return config_of(pcidev_on_root(0, 0));
if (dev)
return config_of(dev);
devtree_bug(__func__, devfn);
dev = dev_find_slot(0, devfn);
return config_of(dev);
} }
void scan_smbus(struct device *bus); void scan_smbus(struct device *bus);

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@ -221,7 +221,7 @@ static unsigned long mainboard_write_acpi_tables(
static void mainboard_enable(struct device *dev) static void mainboard_enable(struct device *dev)
{ {
config_t *conf = config_of_path(SA_DEVFN_ROOT); config_t *conf = config_of_soc();
mainboard_set_power_limits(conf); mainboard_set_power_limits(conf);

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@ -23,7 +23,7 @@ void variant_devtree_update(void)
uint32_t sku_id; uint32_t sku_id;
struct device *emmc_host; struct device *emmc_host;
struct device *ssd_host; struct device *ssd_host;
config_t *cfg = config_of_path(SA_DEVFN_ROOT); config_t *cfg = config_of_soc();
emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC); emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC);
ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA); ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA);

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@ -23,7 +23,7 @@ void variant_devtree_update(void)
uint32_t sku_id; uint32_t sku_id;
struct device *emmc_host; struct device *emmc_host;
struct device *ssd_host; struct device *ssd_host;
config_t *cfg = config_of_path(SA_DEVFN_ROOT); config_t *cfg = config_of_soc();
emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC); emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC);
ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA); ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA);

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@ -39,7 +39,7 @@ static uint32_t get_pl2(void)
/* Override dev tree settings per board */ /* Override dev tree settings per board */
void variant_devtree_update(void) void variant_devtree_update(void)
{ {
config_t *cfg = config_of_path(SA_DEVFN_ROOT); config_t *cfg = config_of_soc();
/* Update PL2 based on CPU */ /* Update PL2 based on CPU */
cfg->tdp_pl2_override = get_pl2(); cfg->tdp_pl2_override = get_pl2();

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@ -241,7 +241,7 @@ void variant_devtree_update(void)
uint8_t pl2_id = PL2_ID_DEFAULT; uint8_t pl2_id = PL2_ID_DEFAULT;
struct device *spi_fpmcu = PCH_DEV_GSPI1; struct device *spi_fpmcu = PCH_DEV_GSPI1;
config_t *cfg = config_of_path(SA_DEVFN_ROOT); config_t *cfg = config_of_soc();
switch (sku_id) { switch (sku_id) {
case SKU_0_SONA: case SKU_0_SONA:

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@ -44,7 +44,7 @@ void variant_devtree_update(void)
uint16_t abase; uint16_t abase;
uint32_t val32; uint32_t val32;
config_t *cfg = config_of_path(SA_DEVFN_ROOT); config_t *cfg = config_of_soc();
switch (sku_id) { switch (sku_id) {
case SKU_0_NAUTILUS: case SKU_0_NAUTILUS:

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@ -40,7 +40,7 @@ static uint32_t get_pl2(void)
/* Override dev tree settings per board */ /* Override dev tree settings per board */
void variant_devtree_update(void) void variant_devtree_update(void)
{ {
config_t *cfg = config_of_path(SA_DEVFN_ROOT); config_t *cfg = config_of_soc();
/* Update PL2 based on CPU */ /* Update PL2 based on CPU */
cfg->tdp_pl2_override = get_pl2(); cfg->tdp_pl2_override = get_pl2();

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@ -90,7 +90,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries)
void acpi_create_gnvs(struct global_nvs_t *gnvs) void acpi_create_gnvs(struct global_nvs_t *gnvs)
{ {
struct soc_intel_apollolake_config *cfg; struct soc_intel_apollolake_config *cfg;
cfg = config_of_path(SA_DEVFN_ROOT); cfg = config_of_soc();
/* Clear out GNVS. */ /* Clear out GNVS. */
memset(gnvs, 0, sizeof(*gnvs)); memset(gnvs, 0, sizeof(*gnvs));
@ -152,7 +152,7 @@ int soc_madt_sci_irq_polarity(int sci)
void soc_fill_fadt(acpi_fadt_t *fadt) void soc_fill_fadt(acpi_fadt_t *fadt)
{ {
const struct soc_intel_apollolake_config *cfg; const struct soc_intel_apollolake_config *cfg;
cfg = config_of_path(SA_DEVFN_ROOT); cfg = config_of_soc();
fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR; fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR;

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@ -300,7 +300,7 @@ static void set_power_limits(void)
uint32_t tdp, min_power, max_power; uint32_t tdp, min_power, max_power;
uint32_t pl2_val; uint32_t pl2_val;
cfg = config_of_path(SA_DEVFN_ROOT); cfg = config_of_soc();
if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
printk(BIOS_INFO, "Skip the RAPL settings.\n"); printk(BIOS_INFO, "Skip the RAPL settings.\n");
@ -364,7 +364,7 @@ static void set_sci_irq(void)
struct soc_intel_apollolake_config *cfg; struct soc_intel_apollolake_config *cfg;
uint32_t scis; uint32_t scis;
cfg = config_of_path(SA_DEVFN_ROOT); cfg = config_of_soc();
/* Change only if a device tree entry exists. */ /* Change only if a device tree entry exists. */
if (cfg->sci_irq) { if (cfg->sci_irq) {

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@ -296,7 +296,7 @@ void cpu_lock_sgx_memory(void)
int soc_fill_sgx_param(struct sgx_param *sgx_param) int soc_fill_sgx_param(struct sgx_param *sgx_param)
{ {
config_t *conf = config_of_path(SA_DEVFN_ROOT); config_t *conf = config_of_soc();
sgx_param->enable = conf->sgx_enable; sgx_param->enable = conf->sgx_enable;
return 0; return 0;

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@ -35,7 +35,7 @@ void *cbmem_top(void)
if (!CONFIG(SOC_INTEL_GLK)) if (!CONFIG(SOC_INTEL_GLK))
return tolum; return tolum;
config = config_of_path(PCH_DEVFN_LPC); config = config_of_soc();
/* FSP allocates 2x PRMRR Size Memory for alignment */ /* FSP allocates 2x PRMRR Size Memory for alignment */
if (config->sgx_enable) if (config->sgx_enable)

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@ -148,7 +148,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
{ {
DEVTREE_CONST struct soc_intel_apollolake_config *config; DEVTREE_CONST struct soc_intel_apollolake_config *config;
config = config_of_path(SA_DEVFN_ROOT); config = config_of_soc();
/* Assign to out variable */ /* Assign to out variable */
*dw0 = config->gpe0_dw1; *dw0 = config->gpe0_dw1;

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@ -39,7 +39,7 @@ static void pnp_settings(void *unused)
const struct pnpconfig *pnpconfigarr; const struct pnpconfig *pnpconfigarr;
struct soc_intel_apollolake_config *config; struct soc_intel_apollolake_config *config;
config = config_of_path(SA_DEVFN_ROOT); config = config_of_soc();
switch (config->pnp_settings) { switch (config->pnp_settings) {
case PNP_PERF: case PNP_PERF:

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@ -95,7 +95,7 @@ static void soc_early_romstage_init(void)
static void configure_thermal_target(void) static void configure_thermal_target(void)
{ {
msr_t msr; msr_t msr;
const config_t *conf = config_of_path(SA_DEVFN_ROOT); const config_t *conf = config_of_soc();
if (!conf->tcc_offset) if (!conf->tcc_offset)
return; return;
@ -269,7 +269,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd)
/* Only for GLK */ /* Only for GLK */
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
const config_t *config = config_of_path(PCH_DEVFN_LPC); const config_t *config = config_of_soc();
m_cfg->PrmrrSize = config->PrmrrSize; m_cfg->PrmrrSize = config->PrmrrSize;

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@ -390,7 +390,7 @@ static void generate_C_state_entries(void)
int *set; int *set;
int i; int i;
config_t *config = config_of_path(SA_DEVFN_ROOT); config_t *config = config_of_soc();
if (config->s0ix_enable) if (config->s0ix_enable)
set = cstate_set_s0ix; set = cstate_set_s0ix;

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@ -196,7 +196,7 @@ static int pcode_mailbox_write(u32 command, u32 data)
static void initialize_vr_config(void) static void initialize_vr_config(void)
{ {
config_t *conf = config_of_path(SA_DEVFN_ROOT); config_t *conf = config_of_soc();
msr_t msr; msr_t msr;
printk(BIOS_DEBUG, "Initializing VR config.\n"); printk(BIOS_DEBUG, "Initializing VR config.\n");
@ -450,7 +450,7 @@ static void configure_c_states(void)
static void configure_thermal_target(void) static void configure_thermal_target(void)
{ {
config_t *conf = config_of_path(SA_DEVFN_ROOT); config_t *conf = config_of_soc();
msr_t msr; msr_t msr;

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@ -78,7 +78,7 @@ static void pch_enable_lpc(void)
/* Lookup device tree in romstage */ /* Lookup device tree in romstage */
const config_t *config; const config_t *config;
config = config_of_path(PCH_DEVFN_LPC); config = config_of_soc();
pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec);
pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec);

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@ -145,7 +145,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries)
int *set; int *set;
int i; int i;
config_t *config = config_of_path(SA_DEVFN_ROOT); config_t *config = config_of_soc();
int is_s0ix_enable = config->s0ix_enable; int is_s0ix_enable = config->s0ix_enable;
@ -166,7 +166,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries)
void soc_power_states_generation(int core_id, int cores_per_package) void soc_power_states_generation(int core_id, int cores_per_package)
{ {
config_t *config = config_of_path(SA_DEVFN_ROOT); config_t *config = config_of_soc();
/* Generate P-state tables */ /* Generate P-state tables */
if (config->eist_enable) if (config->eist_enable)
@ -177,7 +177,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
{ {
const uint16_t pmbase = ACPI_BASE_ADDRESS; const uint16_t pmbase = ACPI_BASE_ADDRESS;
const struct soc_intel_cannonlake_config *config; const struct soc_intel_cannonlake_config *config;
config = config_of_path(PCH_DEVFN_LPC); config = config_of_soc();
if (!config->PmTimerDisabled) { if (!config->PmTimerDisabled) {
fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->pm_tmr_blk = pmbase + PM1_TMR;
@ -202,7 +202,7 @@ uint32_t soc_read_sci_irq_select(void)
void acpi_create_gnvs(struct global_nvs_t *gnvs) void acpi_create_gnvs(struct global_nvs_t *gnvs)
{ {
const struct soc_intel_cannonlake_config *config; const struct soc_intel_cannonlake_config *config;
config = config_of_path(PCH_DEVFN_LPC); config = config_of_soc();
/* Set unknown wake source */ /* Set unknown wake source */
gnvs->pm1i = -1; gnvs->pm1i = -1;

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@ -170,7 +170,7 @@ void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads)
static void soc_fill_gpio_pm_configuration(void) static void soc_fill_gpio_pm_configuration(void)
{ {
uint8_t value[TOTAL_GPIO_COMM]; uint8_t value[TOTAL_GPIO_COMM];
const config_t *config = config_of_path(SA_DEVFN_ROOT); const config_t *config = config_of_soc();
if (config->gpio_override_pm) if (config->gpio_override_pm)
memcpy(value, config->gpio_pm, sizeof(uint8_t) * memcpy(value, config->gpio_pm, sizeof(uint8_t) *

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@ -106,7 +106,7 @@ void set_power_limits(u8 power_limit_1_time)
unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1;
u8 power_limit_1_val; u8 power_limit_1_val;
config_t *conf = config_of_path(SA_DEVFN_ROOT); config_t *conf = config_of_soc();
if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr))
power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1;
@ -234,7 +234,7 @@ static void soc_fsp_load(void)
static void configure_isst(void) static void configure_isst(void)
{ {
config_t *conf = config_of_path(SA_DEVFN_ROOT); config_t *conf = config_of_soc();
msr_t msr; msr_t msr;
if (conf->speed_shift_enable) { if (conf->speed_shift_enable) {
@ -259,7 +259,7 @@ static void configure_isst(void)
static void configure_misc(void) static void configure_misc(void)
{ {
config_t *conf = config_of_path(SA_DEVFN_ROOT); config_t *conf = config_of_soc();
msr_t msr; msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE); msr = rdmsr(IA32_MISC_ENABLE);
@ -361,7 +361,7 @@ static void configure_c_states(void)
static void configure_thermal_target(void) static void configure_thermal_target(void)
{ {
config_t *conf = config_of_path(SA_DEVFN_ROOT); config_t *conf = config_of_soc();
msr_t msr; msr_t msr;
/* Set TCC activation offset if supported */ /* Set TCC activation offset if supported */
@ -387,7 +387,7 @@ static void enable_pm_timer_emulation(void)
const struct soc_intel_cannonlake_config *config; const struct soc_intel_cannonlake_config *config;
msr_t msr; msr_t msr;
config = config_of_path(SA_DEVFN_ROOT); config = config_of_soc();
/* Enable PM timer emulation only if ACPI PM timer is disabled */ /* Enable PM timer emulation only if ACPI PM timer is disabled */
if (!config->PmTimerDisabled) if (!config->PmTimerDisabled)

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@ -84,7 +84,7 @@ static void pch_finalize(void)
* point and hence removed from the root bus. pcidev_path_on_root thus * point and hence removed from the root bus. pcidev_path_on_root thus
* returns NULL for PCH_DEV_PMC device. * returns NULL for PCH_DEV_PMC device.
*/ */
config = config_of_path(SA_DEVFN_ROOT); config = config_of_soc();
pmcbase = pmc_mmio_regs(); pmcbase = pmc_mmio_regs();
if (config->PmTimerDisabled) { if (config->PmTimerDisabled) {
reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);

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@ -99,7 +99,7 @@ static void parse_devicetree_param(const config_t *config, FSP_S_CONFIG *params)
static void parse_devicetree(FSP_S_CONFIG *params) static void parse_devicetree(FSP_S_CONFIG *params)
{ {
const config_t *config = config_of_path(SA_DEVFN_ROOT); const config_t *config = config_of_soc();
parse_devicetree_param(config, params); parse_devicetree_param(config, params);
} }
@ -145,7 +145,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
struct device *dev; struct device *dev;
config_t *config = config_of_path(SA_DEVFN_ROOT); config_t *config = config_of_soc();
/* Parse device tree and enable/disable devices */ /* Parse device tree and enable/disable devices */
parse_devicetree(params); parse_devicetree(params);

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@ -102,7 +102,7 @@ static void config_deep_sx(uint32_t deepsx_config)
static void pmc_init(void *unused) static void pmc_init(void *unused)
{ {
const config_t *config = config_of_path(SA_DEVFN_ROOT); const config_t *config = config_of_soc();
rtc_init(); rtc_init();

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@ -175,7 +175,7 @@ uintptr_t soc_read_pmc_base(void)
void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
{ {
DEVTREE_CONST struct soc_intel_cannonlake_config *config; DEVTREE_CONST struct soc_intel_cannonlake_config *config;
config = config_of_path(SA_DEVFN_ROOT); config = config_of_soc();
/* Assign to out variable */ /* Assign to out variable */
*dw0 = config->gpe0_dw0; *dw0 = config->gpe0_dw0;

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@ -79,7 +79,7 @@ void smihandler_soc_at_finalize(void)
{ {
const struct soc_intel_cannonlake_config *config; const struct soc_intel_cannonlake_config *config;
config = config_of_path(PCH_DEVFN_CSE); config = config_of_soc();
if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
pch_disable_heci(); pch_disable_heci();

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@ -22,7 +22,7 @@ const struct soc_intel_common_config *chip_get_common_soc_structure(void)
const struct soc_intel_common_config *soc_config; const struct soc_intel_common_config *soc_config;
const config_t *config; const config_t *config;
config = config_of_path(SA_DEVFN_ROOT); config = config_of_soc();
soc_config = &config->common_soc_config; soc_config = &config->common_soc_config;
return soc_config; return soc_config;

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@ -24,7 +24,7 @@
static void iou_init(struct device *dev) static void iou_init(struct device *dev)
{ {
/* Use config from device always present in static devicetree. */ /* Use config from device always present in static devicetree. */
const config_t *config = config_of_path(SOC_DEV_FUNC); const config_t *config = config_of_soc();
u16 devctl2; u16 devctl2;
/* pcie completion timeout /* pcie completion timeout

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@ -138,7 +138,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries)
int *set; int *set;
int i; int i;
config_t *config = config_of_path(SA_DEVFN_ROOT); config_t *config = config_of_soc();
int is_s0ix_enable = config->s0ix_enable; int is_s0ix_enable = config->s0ix_enable;
@ -159,7 +159,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries)
void soc_power_states_generation(int core_id, int cores_per_package) void soc_power_states_generation(int core_id, int cores_per_package)
{ {
config_t *config = config_of_path(SA_DEVFN_ROOT); config_t *config = config_of_soc();
if (config->eist_enable) if (config->eist_enable)
/* Generate P-state tables */ /* Generate P-state tables */
@ -170,7 +170,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
{ {
const uint16_t pmbase = ACPI_BASE_ADDRESS; const uint16_t pmbase = ACPI_BASE_ADDRESS;
config_t *config = config_of_path(SA_DEVFN_ROOT); config_t *config = config_of_soc();
if (!config->PmTimerDisabled) { if (!config->PmTimerDisabled) {
fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->pm_tmr_blk = pmbase + PM1_TMR;
@ -194,7 +194,7 @@ uint32_t soc_read_sci_irq_select(void)
void acpi_create_gnvs(struct global_nvs_t *gnvs) void acpi_create_gnvs(struct global_nvs_t *gnvs)
{ {
config_t *config = config_of_path(SA_DEVFN_ROOT); config_t *config = config_of_soc();
/* Set unknown wake source */ /* Set unknown wake source */
gnvs->pm1i = -1; gnvs->pm1i = -1;

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@ -107,7 +107,7 @@ const char *soc_acpi_name(const struct device *dev)
static void soc_fill_gpio_pm_configuration(void) static void soc_fill_gpio_pm_configuration(void)
{ {
uint8_t value[TOTAL_GPIO_COMM]; uint8_t value[TOTAL_GPIO_COMM];
const config_t *config = config_of_path(SA_DEVFN_ROOT); const config_t *config = config_of_soc();
if (config->gpio_override_pm) if (config->gpio_override_pm)
memcpy(value, config->gpio_pm, sizeof(uint8_t) * memcpy(value, config->gpio_pm, sizeof(uint8_t) *

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@ -40,7 +40,7 @@ static void soc_fsp_load(void)
static void configure_isst(void) static void configure_isst(void)
{ {
config_t *conf = config_of_path(SA_DEVFN_ROOT); config_t *conf = config_of_soc();
msr_t msr; msr_t msr;
if (conf->speed_shift_enable) { if (conf->speed_shift_enable) {
@ -67,7 +67,7 @@ static void configure_misc(void)
{ {
msr_t msr; msr_t msr;
config_t *conf = config_of_path(SA_DEVFN_ROOT); config_t *conf = config_of_soc();
msr = rdmsr(IA32_MISC_ENABLE); msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 0); /* Fast String enable */

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@ -83,7 +83,7 @@ static void pch_finalize(void)
* point and hence removed from the root bus. pcidev_path_on_root thus * point and hence removed from the root bus. pcidev_path_on_root thus
* returns NULL for PCH_DEV_PMC device. * returns NULL for PCH_DEV_PMC device.
*/ */
config = config_of_path(SA_DEVFN_ROOT); config = config_of_soc();
pmcbase = pmc_mmio_regs(); pmcbase = pmc_mmio_regs();
if (config->PmTimerDisabled) { if (config->PmTimerDisabled) {
reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);

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@ -31,7 +31,7 @@
static void parse_devicetree(FSP_S_CONFIG *params) static void parse_devicetree(FSP_S_CONFIG *params)
{ {
const struct soc_intel_icelake_config *config; const struct soc_intel_icelake_config *config;
config = config_of_path(SA_DEVFN_ROOT); config = config_of_soc();
for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
@ -69,7 +69,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
struct device *dev; struct device *dev;
struct soc_intel_icelake_config *config; struct soc_intel_icelake_config *config;
config = config_of_path(SA_DEVFN_ROOT); config = config_of_soc();
/* Parse device tree and enable/disable devices */ /* Parse device tree and enable/disable devices */
parse_devicetree(params); parse_devicetree(params);

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@ -84,7 +84,7 @@ static void config_deep_sx(uint32_t deepsx_config)
static void pmc_init(void *unused) static void pmc_init(void *unused)
{ {
const config_t *config = config_of_path(SA_DEVFN_ROOT); const config_t *config = config_of_soc();
rtc_init(); rtc_init();

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@ -174,7 +174,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
{ {
DEVTREE_CONST struct soc_intel_icelake_config *config; DEVTREE_CONST struct soc_intel_icelake_config *config;
config = config_of_path(SA_DEVFN_ROOT); config = config_of_soc();
/* Assign to out variable */ /* Assign to out variable */
*dw0 = config->gpe0_dw0; *dw0 = config->gpe0_dw0;

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@ -79,7 +79,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
const struct soc_intel_icelake_config *config; const struct soc_intel_icelake_config *config;
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
config = config_of_path(SA_DEVFN_ROOT); config = config_of_soc();
soc_memory_init_params(m_cfg, config); soc_memory_init_params(m_cfg, config);

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@ -76,7 +76,7 @@ void smihandler_soc_at_finalize(void)
{ {
const struct soc_intel_icelake_config *config; const struct soc_intel_icelake_config *config;
config = config_of_path(PCH_DEVFN_CSE); config = config_of_soc();
if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
pch_disable_heci(); pch_disable_heci();

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@ -93,7 +93,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version)
"Microcode file (rmu.bin) not found."); "Microcode file (rmu.bin) not found.");
/* Locate the configuration data from devicetree.cb */ /* Locate the configuration data from devicetree.cb */
config = config_of_path(LPC_DEV_FUNC); config = config_of_soc();
/* Update the architectural UPD values. */ /* Update the architectural UPD values. */
aupd = &fspm_upd->FspmArchUpd; aupd = &fspm_upd->FspmArchUpd;

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@ -172,7 +172,7 @@ static int get_cores_per_package(void)
static void acpi_create_gnvs(global_nvs_t *gnvs) static void acpi_create_gnvs(global_nvs_t *gnvs)
{ {
const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = config_of_soc();
/* Set unknown wake source */ /* Set unknown wake source */
gnvs->pm1i = -1; gnvs->pm1i = -1;
@ -232,7 +232,7 @@ unsigned long acpi_fill_madt(unsigned long current)
void acpi_fill_fadt(acpi_fadt_t *fadt) void acpi_fill_fadt(acpi_fadt_t *fadt)
{ {
const uint16_t pmbase = ACPI_BASE_ADDRESS; const uint16_t pmbase = ACPI_BASE_ADDRESS;
config_t *config = config_of_path(SA_DEVFN_ROOT); config_t *config = config_of_soc();
/* Use ACPI 3.0 revision */ /* Use ACPI 3.0 revision */
fadt->header.revision = get_acpi_table_revision(FADT); fadt->header.revision = get_acpi_table_revision(FADT);
@ -503,7 +503,7 @@ void generate_cpu_entries(struct device *device)
int totalcores = dev_count_cpu(); int totalcores = dev_count_cpu();
int cores_per_package = get_cores_per_package(); int cores_per_package = get_cores_per_package();
int numcpus = totalcores/cores_per_package; int numcpus = totalcores/cores_per_package;
config_t *config = config_of_path(SA_DEVFN_ROOT); config_t *config = config_of_soc();
int is_s0ix_enable = config->s0ix_enable; int is_s0ix_enable = config->s0ix_enable;
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
@ -674,7 +674,7 @@ void southbridge_inject_dsdt(struct device *device)
/* Save wake source information for calculating ACPI _SWS values */ /* Save wake source information for calculating ACPI _SWS values */
int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
{ {
const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = config_of_soc();
struct chipset_power_state *ps; struct chipset_power_state *ps;
static uint32_t gpe0_sts[GPE0_REG_MAX]; static uint32_t gpe0_sts[GPE0_REG_MAX];
uint32_t pm1_en; uint32_t pm1_en;

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@ -237,7 +237,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
uintptr_t vbt_data = (uintptr_t)vbt_get(); uintptr_t vbt_data = (uintptr_t)vbt_get();
int i; int i;
config = config_of_path(SA_DEVFN_ROOT); config = config_of_soc();
mainboard_silicon_init_params(params); mainboard_silicon_init_params(params);
/* Set PsysPmax if it is available from DT */ /* Set PsysPmax if it is available from DT */

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@ -117,7 +117,7 @@ void set_power_limits(u8 power_limit_1_time)
unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1;
u8 power_limit_1_val; u8 power_limit_1_val;
config_t *conf = config_of_path(SA_DEVFN_ROOT); config_t *conf = config_of_soc();
if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr))
power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1;
@ -240,7 +240,7 @@ void set_power_limits(u8 power_limit_1_time)
static void configure_thermal_target(void) static void configure_thermal_target(void)
{ {
config_t *conf = config_of_path(SA_DEVFN_ROOT); config_t *conf = config_of_soc();
msr_t msr; msr_t msr;
@ -260,7 +260,7 @@ static void configure_thermal_target(void)
static void configure_isst(void) static void configure_isst(void)
{ {
config_t *conf = config_of_path(SA_DEVFN_ROOT); config_t *conf = config_of_soc();
msr_t msr; msr_t msr;
@ -286,7 +286,7 @@ static void configure_isst(void)
static void configure_misc(void) static void configure_misc(void)
{ {
config_t *conf = config_of_path(SA_DEVFN_ROOT); config_t *conf = config_of_soc();
msr_t msr; msr_t msr;
@ -562,7 +562,7 @@ void cpu_lock_sgx_memory(void)
int soc_fill_sgx_param(struct sgx_param *sgx_param) int soc_fill_sgx_param(struct sgx_param *sgx_param)
{ {
config_t *conf = config_of_path(SA_DEVFN_ROOT); config_t *conf = config_of_soc();
sgx_param->enable = conf->sgx_enable; sgx_param->enable = conf->sgx_enable;
return 0; return 0;

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@ -188,7 +188,7 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
*/ */
static void pm1_handle_wake_pin(void *unused) static void pm1_handle_wake_pin(void *unused)
{ {
const config_t *conf = config_of_path(SA_DEVFN_ROOT); const config_t *conf = config_of_soc();
/* If WAKE# pin is enabled, bail out early. */ /* If WAKE# pin is enabled, bail out early. */
if (conf->deep_sx_config & DSX_EN_WAKE_PIN) if (conf->deep_sx_config & DSX_EN_WAKE_PIN)

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@ -177,7 +177,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
{ {
DEVTREE_CONST struct soc_intel_skylake_config *config; DEVTREE_CONST struct soc_intel_skylake_config *config;
config = config_of_path(PCH_DEVFN_PMC); config = config_of_soc();
/* Assign to out variable */ /* Assign to out variable */
*dw0 = config->gpe0_dw0; *dw0 = config->gpe0_dw0;

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@ -43,7 +43,7 @@ void soc_pre_ram_init(struct romstage_params *params)
/* Program MCHBAR and DMIBAR */ /* Program MCHBAR and DMIBAR */
systemagent_early_init(); systemagent_early_init();
config = config_of_path(PCH_DEVFN_LPC); config = config_of_soc();
/* Force a full memory train if RMT is enabled */ /* Force a full memory train if RMT is enabled */
params->disable_saved_data = config->Rmt; params->disable_saved_data = config->Rmt;
@ -57,7 +57,7 @@ void soc_memory_init_params(struct romstage_params *params,
/* Set the parameters for MemoryInit */ /* Set the parameters for MemoryInit */
config = config_of_path(PCH_DEVFN_LPC); config = config_of_soc();
/* /*
* Set IGD stolen size to 64MB. The FBC hardware for skylake does not * Set IGD stolen size to 64MB. The FBC hardware for skylake does not

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@ -289,7 +289,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
config = config_of_path(PCH_DEVFN_LPC); config = config_of_soc();
soc_memory_init_params(m_cfg, config); soc_memory_init_params(m_cfg, config);
soc_peg_init_params(m_cfg, m_t_cfg, config); soc_peg_init_params(m_cfg, m_t_cfg, config);

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@ -29,7 +29,7 @@ static void systemagent_vtd_init(void)
const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
const struct soc_intel_skylake_config *config = NULL; const struct soc_intel_skylake_config *config = NULL;
config = config_of_path(SA_DEVFN_ROOT); config = config_of_soc();
if (config->ignore_vtd) if (config->ignore_vtd)
return; return;