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Whitespace cleanup (trivial). 

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson 2008-10-02 19:20:22 +00:00
parent 7f3d48c9af
commit d61ada6555
18 changed files with 2656 additions and 2655 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/northbridge/amd/amdk8/Config.lb
View File

@ -19,13 +19,13 @@ end
if HAVE_ACPI_TABLES
object amdk8_acpi.o
makerule ssdt.c
depends "$(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"
action "iasl -p $(PWD)/ssdt -tc $(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex"
action "mv ssdt.hex ssdt.c"
end
object ./ssdt.o
makerule ssdt.c
depends "$(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"
action "iasl -p $(PWD)/ssdt -tc $(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex"
action "mv ssdt.hex ssdt.c"
end
object ./ssdt.o
end

288
src/northbridge/amd/amdk8/amdk8_acpi.c
View File

@ -49,133 +49,131 @@ acknowledgement of AMD's proprietary rights in them.
unsigned long acpi_create_madt_lapics(unsigned long current)
{
device_t cpu;
int cpu_index = 0;
device_t cpu;
int cpu_index = 0;
for(cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
{
continue;
}
if (!cpu->enabled) {
continue;
}
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.u.apic.apic_id);
cpu_index++;
for(cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
{
continue;
}
if (!cpu->enabled) {
continue;
}
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.u.apic.apic_id);
cpu_index++;
}
}
return current;
return current;
}
unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint)
{
device_t cpu;
int cpu_index = 0;
device_t cpu;
int cpu_index = 0;
for(cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
{
continue;
}
if (!cpu->enabled) {
continue;
}
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint);
cpu_index++;
for(cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
{
continue;
}
if (!cpu->enabled) {
continue;
}
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint);
cpu_index++;
}
}
return current;
return current;
}
unsigned long acpi_create_srat_lapics(unsigned long current)
{
device_t cpu;
int cpu_index = 0;
device_t cpu;
int cpu_index = 0;
for(cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
{
continue;
}
if (!cpu->enabled) {
continue;
}
printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id);
current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id);
cpu_index++;
for(cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
{
continue;
}
if (!cpu->enabled) {
continue;
}
printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id);
current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id);
cpu_index++;
}
}
return current;
return current;
}
static unsigned long resk(uint64_t value)
{
unsigned long resultk;
if (value < (1ULL << 42)) {
resultk = value >> 10;
}
else {
resultk = 0xffffffff;
}
return resultk;
unsigned long resultk;
if (value < (1ULL << 42)) {
resultk = value >> 10;
}
else {
resultk = 0xffffffff;
}
return resultk;
}
struct acpi_srat_mem_state {
unsigned long current;
unsigned long current;
};
void set_srat_mem(void *gp, struct device *dev, struct resource *res)
{
struct acpi_srat_mem_state *state = gp;
unsigned long basek, sizek;
basek = resk(res->base);
sizek = resk(res->size);
struct acpi_srat_mem_state *state = gp;
unsigned long basek, sizek;
basek = resk(res->base);
sizek = resk(res->size);
printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n",
dev_path(dev), res->index, basek, sizek);
/*
0-640K must be on node 0
next range is from 1M---
So will cut off before 1M in the mem range
*/
if((basek+sizek)<1024) return;
printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n",
dev_path(dev), res->index, basek, sizek);
/*
0-640K must be on node 0
next range is from 1M---
So will cut off before 1M in the mem range
*/
if((basek+sizek)<1024) return;
if(basek<1024) {
sizek -= 1024 - basek;
basek = 1024;
}
if(basek<1024) {
sizek -= 1024 - basek;
basek = 1024;
}
state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); // need to figure out NV
state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); // need to figure out NV
}
unsigned long acpi_fill_srat(unsigned long current)
{
struct acpi_srat_mem_state srat_mem_state;
struct acpi_srat_mem_state srat_mem_state;
/* create all subtables for processors */
current = acpi_create_srat_lapics(current);
/* create all subtables for processors */
current = acpi_create_srat_lapics(current);
/* create all subteble for memory range */
/* create all subteble for memory range */
/* 0-640K must be on node 0 */
current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable
#if 1
srat_mem_state.current = current;
search_global_resources(
IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
set_srat_mem, &srat_mem_state);
/* 0-640K must be on node 0 */
current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable
current = srat_mem_state.current;
#endif
return current;
srat_mem_state.current = current;
search_global_resources(
IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
set_srat_mem, &srat_mem_state);
current = srat_mem_state.current;
return current;
}
@ -184,7 +182,7 @@ unsigned long acpi_fill_slit(unsigned long current)
/* need to find out the node num at first */
/* fill the first 8 byte with that num */
/* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */
/* because We has assume that we know the topology of the HT connection, So we can have set if we know the node_num */
static uint8_t hops_8[] = { 0, 1, 1, 2, 2, 3, 3, 4,
1, 0, 2, 1, 3, 2, 4, 3,
@ -192,7 +190,7 @@ unsigned long acpi_fill_slit(unsigned long current)
2, 1, 1, 0, 2, 1, 3, 2,
2, 3, 1, 2, 0, 1, 1, 2,
3, 2, 2, 1, 1, 0, 2, 1,
3, 4, 2, 3, 1, 2, 0, 1,
3, 4, 2, 3, 1, 2, 0, 1,
4, 4, 3, 2, 2, 1, 1, 0 };
// uint8_t outer_node[8];
@ -208,10 +206,10 @@ unsigned long acpi_fill_slit(unsigned long current)
#if 0
for(i=0;i<sysconf.hc_possible_num;i++) {
if((sysconf.pci1234[i]&1) !=1 ) continue;
outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node
outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node
}
#endif
for(i=0;i<nodes;i++) {
for(j=0;j<nodes; j++) {
if(i==j) { p[i*nodes+j] = 10; }
@ -234,7 +232,7 @@ unsigned long acpi_fill_slit(unsigned long current)
}
}
p[i*nodes+j] = hops_8[i*nodes+j] * 2 + latency_factor + 10;
#else
#else
p[i*nodes+j] = hops_8[i*nodes+j] * 2 + 10;
#endif
@ -243,9 +241,9 @@ unsigned long acpi_fill_slit(unsigned long current)
}
}
current += 8+nodes*nodes;
current += 8+nodes*nodes;
return current;
return current;
}
@ -255,10 +253,10 @@ unsigned long acpi_fill_slit(unsigned long current)
// moved from mb acpi_tables.c
static void int_to_stream(uint32_t val, uint8_t *dest)
{
int i;
for(i=0;i<4;i++) {
*(dest+i) = (val >> (8*i)) & 0xff;
}
int i;
for(i=0;i<4;i++) {
*(dest+i) = (val >> (8*i)) & 0xff;
}
}
@ -266,60 +264,60 @@ static void int_to_stream(uint32_t val, uint8_t *dest)
void update_ssdt(void *ssdt)
{
uint8_t *BUSN;
uint8_t *MMIO;
uint8_t *PCIO;
uint8_t *SBLK;
uint8_t *TOM1;
uint8_t *SBDN;
uint8_t *HCLK;
uint8_t *HCDN;
uint8_t *BUSN;
uint8_t *MMIO;
uint8_t *PCIO;
uint8_t *SBLK;
uint8_t *TOM1;
uint8_t *SBDN;
uint8_t *HCLK;
uint8_t *HCDN;
uint8_t *CBST;
int i;
device_t dev;
uint32_t dword;
msr_t msr;
int i;
device_t dev;
uint32_t dword;
msr_t msr;
BUSN = ssdt+0x3a; //+5 will be next BUSN
MMIO = ssdt+0x57; //+5 will be next MMIO
PCIO = ssdt+0xaf; //+5 will be next PCIO
SBLK = ssdt+0xdc; // one byte
TOM1 = ssdt+0xe3; //
SBDN = ssdt+0xed;//
HCLK = ssdt+0xfa; //+5 will be next HCLK
HCDN = ssdt+0x12a; //+5 will be next HCDN
BUSN = ssdt+0x3a; //+5 will be next BUSN
MMIO = ssdt+0x57; //+5 will be next MMIO
PCIO = ssdt+0xaf; //+5 will be next PCIO
SBLK = ssdt+0xdc; // one byte
TOM1 = ssdt+0xe3; //
SBDN = ssdt+0xed; //
HCLK = ssdt+0xfa; //+5 will be next HCLK
HCDN = ssdt+0x12a; //+5 will be next HCDN
CBST = ssdt+0x157; //
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
for(i=0;i<4;i++) {
dword = pci_read_config32(dev, 0xe0+i*4);
int_to_stream(dword, BUSN+i*5);
}
for(i=0;i<0x10;i++) {
dword = pci_read_config32(dev, 0x80+i*4);
int_to_stream(dword, MMIO+i*5);
}
for(i=0;i<0x08;i++) {
dword = pci_read_config32(dev, 0xc0+i*4);
int_to_stream(dword, PCIO+i*5);
}
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
for(i=0;i<4;i++) {
dword = pci_read_config32(dev, 0xe0+i*4);
int_to_stream(dword, BUSN+i*5);
}
for(i=0;i<0x10;i++) {
dword = pci_read_config32(dev, 0x80+i*4);
int_to_stream(dword, MMIO+i*5);
}
for(i=0;i<0x08;i++) {
dword = pci_read_config32(dev, 0xc0+i*4);
int_to_stream(dword, PCIO+i*5);
}
*SBLK = (uint8_t)(sysconf.sblk);
*SBLK = (uint8_t)(sysconf.sblk);
msr = rdmsr(TOP_MEM);
int_to_stream(msr.lo, TOM1);
msr = rdmsr(TOP_MEM);
int_to_stream(msr.lo, TOM1);
for(i=0;i<sysconf.hc_possible_num;i++) {
int_to_stream(sysconf.pci1234[i], HCLK + i*5);
int_to_stream(sysconf.hcdn[i], HCDN + i*5);
}
for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
int_to_stream(0x00000000, HCLK + i*5);
int_to_stream(0x20202020, HCDN + i*5);
}
for(i=0;i<sysconf.hc_possible_num;i++) {
int_to_stream(sysconf.pci1234[i], HCLK + i*5);
int_to_stream(sysconf.hcdn[i], HCDN + i*5);
}
for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
int_to_stream(0x00000000, HCLK + i*5);
int_to_stream(0x20202020, HCDN + i*5);
}
int_to_stream(sysconf.sbdn, SBDN);
int_to_stream(sysconf.sbdn, SBDN);
if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0
*CBST = (uint8_t) (0x0f);

86
src/northbridge/amd/amdk8/amdk8_f.h
View File

@ -461,48 +461,48 @@ that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10,
//struct definitions
struct dimm_size {
uint8_t per_rank; // it is rows + col + bank_lines + data lines */
uint8_t rows;
uint8_t col;
uint8_t bank; //1, 2, 3 mean 2, 4, 8
uint8_t rank;
uint8_t per_rank; // it is rows + col + bank_lines + data lines */
uint8_t rows;
uint8_t col;
uint8_t bank; //1, 2, 3 mean 2, 4, 8
uint8_t rank;
} __attribute__((packed));
struct mem_info { // pernode
uint32_t dimm_mask;
struct dimm_size sz[DIMM_SOCKETS];
uint32_t x4_mask;
uint32_t x16_mask;
uint32_t dimm_mask;
struct dimm_size sz[DIMM_SOCKETS];
uint32_t x4_mask;
uint32_t x16_mask;
uint32_t single_rank_mask;
uint32_t page_1k_mask;
// uint32_t ecc_mask;
// uint32_t registered_mask;
uint8_t is_opteron;
uint8_t is_registered;
uint8_t is_ecc;
uint8_t is_Width128;
uint32_t page_1k_mask;
// uint32_t ecc_mask;
// uint32_t registered_mask;
uint8_t is_opteron;
uint8_t is_registered;
uint8_t is_ecc;
uint8_t is_Width128;
uint8_t is_64MuxMode;
uint8_t memclk_set; // we need to use this to retrieve the mem param
uint8_t memclk_set; // we need to use this to retrieve the mem param
uint8_t rsv[2];
} __attribute__((packed));
struct link_pair_st {
device_t udev;
uint32_t upos;
uint32_t uoffs;
device_t dev;
uint32_t pos;
uint32_t offs;
device_t udev;
uint32_t upos;
uint32_t uoffs;
device_t dev;
uint32_t pos;
uint32_t offs;
} __attribute__((packed));
struct sys_info {
uint8_t ctrl_present[NODE_NUMS];
struct mem_info meminfo[NODE_NUMS];
uint8_t ctrl_present[NODE_NUMS];
struct mem_info meminfo[NODE_NUMS];
struct mem_controller ctrl[NODE_NUMS];
uint8_t mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail
uint32_t tom_k;
uint32_t tom2_k;
uint32_t tom_k;
uint32_t tom2_k;
uint32_t mem_base[NODE_NUMS];
uint32_t cs_base[NODE_NUMS*8]; //8 cs_idx
@ -511,9 +511,9 @@ struct sys_info {
uint8_t dqs_delay_a[NODE_NUMS*2*2*9]; //8 node channel 2, direction 2 , bytelane *9
uint8_t dqs_rcvr_dly_a[NODE_NUMS*2*8]; //8 node, channel 2, receiver 8
uint32_t nodes;
struct link_pair_st link_pair[16];// enough? only in_conherent
uint32_t link_pair_num;
uint32_t ht_c_num;
struct link_pair_st link_pair[16];// enough? only in_conherent
uint32_t link_pair_num;
uint32_t ht_c_num;
uint32_t sbdn;
uint32_t sblk;
uint32_t sbbusn;
@ -526,38 +526,38 @@ static void soft_reset(void);
static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
{
int i;
uint32_t mask = 0;
int i;
uint32_t mask = 0;
unsigned needs_reset = 0;
if(sysinfo->nodes == 1) return; // in case only one cpu installed
for(i=1; i<sysinfo->nodes; i++) {
/* Skip everything if I don't have any memory on this controller */
if(sysinfo->mem_trained[i]==0x00) continue;
for(i=1; i<sysinfo->nodes; i++) {
/* Skip everything if I don't have any memory on this controller */
if(sysinfo->mem_trained[i]==0x00) continue;
mask |= (1<<i);
mask |= (1<<i);
}
}
i = 1;
while(1) {
i = 1;
while(1) {
if(mask & (1<<i)) {
if((sysinfo->mem_trained[i])!=0x80) {
mask &= ~(1<<i);
}
}
if(!mask) break;
if(!mask) break;
#if 0
/* cpu_relax */
__asm__ __volatile__("rep;nop": : :"memory");
#endif
i++;
i%=sysinfo->nodes;
i++;
i%=sysinfo->nodes;
}
for(i=0; i<sysinfo->nodes; i++) {
@ -566,7 +566,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
#else
printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
#endif
switch(sysinfo->mem_trained[i]) {
switch(sysinfo->mem_trained[i]) {
case 0: //don't need train
case 1: //trained
break;

42
src/northbridge/amd/amdk8/amdk8_f_pci.c
View File

@ -4,53 +4,53 @@
/* bit [10,8] are dev func, bit[1,0] are dev index */
static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32_t index)
{
uint32_t dword;
uint32_t dword;
pci_write_config32(dev, index_reg, index);
pci_write_config32(dev, index_reg, index);
dword = pci_read_config32(dev, index_reg+0x4);
dword = pci_read_config32(dev, index_reg+0x4);
return dword;
return dword;
}
static void pci_write_config32_index(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data)
{
pci_write_config32(dev, index_reg, index);
pci_write_config32(dev, index_reg, index);
pci_write_config32(dev, index_reg + 0x4, data);
pci_write_config32(dev, index_reg + 0x4, data);
}
static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index)
{
uint32_t dword;
uint32_t dword;
index &= ~(1<<30);
pci_write_config32(dev, index_reg, index);
index &= ~(1<<30);
pci_write_config32(dev, index_reg, index);
do {
dword = pci_read_config32(dev, index_reg);
} while (!(dword & (1<<31)));
do {
dword = pci_read_config32(dev, index_reg);
} while (!(dword & (1<<31)));
dword = pci_read_config32(dev, index_reg+0x4);
dword = pci_read_config32(dev, index_reg+0x4);
return dword;
return dword;
}
static void pci_write_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data)
{
uint32_t dword;
uint32_t dword;
pci_write_config32(dev, index_reg + 0x4, data);
pci_write_config32(dev, index_reg + 0x4, data);
index |= (1<<30);
pci_write_config32(dev, index_reg, index);
do {
dword = pci_read_config32(dev, index_reg);
} while (!(dword & (1<<31)));
index |= (1<<30);
pci_write_config32(dev, index_reg, index);
do {
dword = pci_read_config32(dev, index_reg);
} while (!(dword & (1<<31)));
}

774
src/northbridge/amd/amdk8/coherent_ht.c
View File

File diff suppressed because it is too large Load Diff

206
src/northbridge/amd/amdk8/debug.c
View File

@ -7,10 +7,10 @@ static inline void print_debug_addr(const char *str, void *val)
{
#if CACHE_AS_RAM_ADDRESS_DEBUG == 1
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("------Address debug: %s%x------\r\n", str, val);
#else
printk_debug("------Address debug: %s%x------\r\n", str, val);
#else
print_debug ("------Address debug: "); print_debug(str); print_debug_hex32(val); print_debug("------\r\n");
#endif
#endif
#endif
}
@ -32,8 +32,8 @@ static void print_debug_pci_dev(unsigned dev)
static void print_pci_devices(void)
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0xff, 0x1f, 0x7);
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0xff, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
@ -64,12 +64,12 @@ static void dump_pci_device(unsigned dev)
{
int i;
print_debug_pci_dev(dev);
for(i = 0; i < 256; i++) {
unsigned char val;
if ((i & 0x0f) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("\r\n%02x:",i);
printk_debug("\r\n%02x:",i);
#else
print_debug("\r\n");
print_debug_hex8(i);
@ -91,40 +91,40 @@ static void dump_pci_device(unsigned dev)
static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index);
static void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
{
int i;
print_debug_pci_dev(dev);
print_debug(" -- index_reg="); print_debug_hex32(index_reg);
int i;
print_debug_pci_dev(dev);
print_debug(" -- index_reg="); print_debug_hex32(index_reg);
for(i = 0; i < 0x40; i++) {
uint32_t val;
for(i = 0; i < 0x40; i++) {
uint32_t val;
int j;
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("\r\n%02x:",i);
printk_debug("\r\n%02x:",i);
#else
print_debug("\r\n");
print_debug_hex8(i);
print_debug_char(':');
print_debug("\r\n");
print_debug_hex8(i);
print_debug_char(':');
#endif
val = pci_read_config32_index_wait(dev, index_reg, i);
val = pci_read_config32_index_wait(dev, index_reg, i);
for(j=0;j<4;j++) {
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug(" %02x", val & 0xff);
printk_debug(" %02x", val & 0xff);
#else
print_debug_char(' '); print_debug_hex8(val&0xff);
print_debug_char(' '); print_debug_hex8(val&0xff);
#endif
val >>= 8;
}
}
print_debug("\r\n");
}
print_debug("\r\n");
}
#endif
static void dump_pci_devices(void)
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0xff, 0x1f, 0x7);
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0xff, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
@ -135,39 +135,39 @@ static void dump_pci_devices(void)
}
dump_pci_device(dev);
if(((dev>>12) & 0x07) == 0) {
uint8_t hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
if((hdr_type & 0x80) != 0x80) {
dev += PCI_DEV(0,0,7);
}
}
if(((dev>>12) & 0x07) == 0) {
uint8_t hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
if((hdr_type & 0x80) != 0x80) {
dev += PCI_DEV(0,0,7);
}
}
}
}
static void dump_pci_devices_on_bus(unsigned busn)
{
device_t dev;
for(dev = PCI_DEV(busn, 0, 0);
dev <= PCI_DEV(busn, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0x0000)) {
continue;
}
dump_pci_device(dev);
device_t dev;
for(dev = PCI_DEV(busn, 0, 0);
dev <= PCI_DEV(busn, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0x0000)) {
continue;
}
dump_pci_device(dev);
if(((dev>>12) & 0x07) == 0) {
uint8_t hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
if((hdr_type & 0x80) != 0x80) {
dev += PCI_DEV(0,0,7);
}
}
}
if(((dev>>12) & 0x07) == 0) {
uint8_t hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
if((hdr_type & 0x80) != 0x80) {
dev += PCI_DEV(0,0,7);
}
}
}
}
#ifndef DEBUG_SMBUS
@ -187,8 +187,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("dimm: %02x.0: %02x", i, device);
#else
print_debug("dimm: ");
print_debug_hex8(i);
print_debug("dimm: ");
print_debug_hex8(i);
print_debug(".0: ");
print_debug_hex8(device);
#endif
@ -222,10 +222,10 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
if (device) {
int j;
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("dimm: %02x.1: %02x", i, device);
printk_debug("dimm: %02x.1: %02x", i, device);
#else
print_debug("dimm: ");
print_debug_hex8(i);
print_debug("dimm: ");
print_debug_hex8(i);
print_debug(".1: ");
print_debug_hex8(device);
#endif
@ -234,7 +234,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
unsigned char byte;
if ((j & 0xf) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("\r\n%02x: ", j);
printk_debug("\r\n%02x: ", j);
#else
print_debug("\r\n");
print_debug_hex8(j);
@ -247,7 +247,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
}
byte = status & 0xff;
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%02x ", byte);
printk_debug("%02x ", byte);
#else
print_debug_hex8(byte);
print_debug_char(' ');
@ -260,89 +260,89 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
static void dump_smbus_registers(void)
{
unsigned device;
print_debug("\r\n");
for(device = 1; device < 0x80; device++) {
int j;
print_debug("\r\n");
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("smbus: %02x", device);
#else
print_debug("smbus: ");
print_debug_hex8(device);
print_debug("smbus: ");
print_debug_hex8(device);
#endif
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
status = smbus_read_byte(device, j);
if (status < 0) {
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
status = smbus_read_byte(device, j);
if (status < 0) {
break;
}
if ((j & 0xf) == 0) {
}
if ((j & 0xf) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("\r\n%02x: ",j);
#else
print_debug("\r\n");
print_debug_hex8(j);
print_debug(": ");
print_debug("\r\n");
print_debug_hex8(j);
print_debug(": ");
#endif
}
byte = status & 0xff;
}
byte = status & 0xff;
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%02x ", byte);
printk_debug("%02x ", byte);
#else
print_debug_hex8(byte);
print_debug_char(' ');
print_debug_hex8(byte);
print_debug_char(' ');
#endif
}
print_debug("\r\n");
}
}
print_debug("\r\n");
}
}
#endif
static void dump_io_resources(unsigned port)
static void dump_io_resources(unsigned port)
{
int i;
udelay(2000);
udelay(2000);
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%04x:\r\n", port);
#else
print_debug_hex16(port);
print_debug(":\r\n");
print_debug_hex16(port);
print_debug(":\r\n");
#endif
for(i=0;i<256;i++) {
uint8_t val;
if ((i & 0x0f) == 0) {
for(i=0;i<256;i++) {
uint8_t val;
if ((i & 0x0f) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%02x:", i);
#else
print_debug_hex8(i);
print_debug_char(':');
print_debug_hex8(i);
print_debug_char(':');
#endif
}
val = inb(port);
}
val = inb(port);
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug(" %02x",val);
#else
print_debug_char(' ');
print_debug_hex8(val);
print_debug_char(' ');
print_debug_hex8(val);
#endif
if ((i & 0x0f) == 0x0f) {
print_debug("\r\n");
}
if ((i & 0x0f) == 0x0f) {
print_debug("\r\n");
}
port++;
}
}
}
static void dump_mem(unsigned start, unsigned end)
{
unsigned i;
unsigned i;
print_debug("dump_mem:");
for(i=start;i<end;i++) {
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("\r\n%08x:", i);
#else
#else
print_debug("\r\n");
print_debug_hex32(i);
print_debug(":");
@ -352,9 +352,9 @@ static void dump_mem(unsigned start, unsigned end)
printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
#else
print_debug(" ");
print_debug_hex8((unsigned char)*((unsigned char *)i));
print_debug_hex8((unsigned char)*((unsigned char *)i));
#endif
}
print_debug("\r\n");
}
print_debug("\r\n");
}
#endif

18
src/northbridge/amd/amdk8/early_ht.c
View File

@ -1,11 +1,11 @@
/*
/*
2005.11 yhlu add let the real sb to use small unitid
*/
// only for sb ht chain
static void enumerate_ht_chain(void)
{
#if HT_CHAIN_UNITID_BASE != 0
/* HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */
#if HT_CHAIN_UNITID_BASE != 0
/* HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */
/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
* On most boards this just happens. If a cpu has multiple
@ -43,7 +43,7 @@ static void enumerate_ht_chain(void)
hdr_type &= 0x7f;
if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
(hdr_type == PCI_HEADER_TYPE_BRIDGE))
(hdr_type == PCI_HEADER_TYPE_BRIDGE))
{
pos = pci_read_config8(dev, PCI_CAPABILITY_LIST);
}
@ -71,7 +71,7 @@ static void enumerate_ht_chain(void)
} else {
goto out;
}
}
}
real_last_unitid = next_unitid;
real_last_pos = pos;
ht_dev_num++;
@ -115,7 +115,7 @@ static void enumerate_ht_chain(void)
}
}
} while((ctrl & (1 << 5)) == 0);
break;
}
}
@ -130,9 +130,9 @@ out:
if((ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used) {
uint16_t flags;
dev = PCI_DEV(0,real_last_unitid, 0);
flags = pci_read_config16(dev, real_last_pos + PCI_CAP_FLAGS);
flags &= ~0x1f;
flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
flags = pci_read_config16(dev, real_last_pos + PCI_CAP_FLAGS);
flags &= ~0x1f;
flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
pci_write_config16(dev, real_last_pos + PCI_CAP_FLAGS, flags);
}
#endif

190
src/northbridge/amd/amdk8/get_sblk_pci1234.c
View File

@ -35,36 +35,36 @@
#if 0
unsigned node_link_to_bus(unsigned node, unsigned link)
{
device_t dev;
unsigned reg;
device_t dev;
unsigned reg;
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
if (!dev) {
return 0;
}
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
uint32_t config_map;
unsigned dst_node;
unsigned dst_link;
unsigned bus_base;
config_map = pci_read_config32(dev, reg);
if ((config_map & 3) != 3) {
continue;
}
dst_node = (config_map >> 4) & 7;
dst_link = (config_map >> 8) & 3;
bus_base = (config_map >> 16) & 0xff;
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
if (!dev) {
return 0;
}
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
uint32_t config_map;
unsigned dst_node;
unsigned dst_link;
unsigned bus_base;
config_map = pci_read_config32(dev, reg);
if ((config_map & 3) != 3) {
continue;
}
dst_node = (config_map >> 4) & 7;
dst_link = (config_map >> 8) & 3;
bus_base = (config_map >> 16) & 0xff;
#if 0
printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
dst_node, dst_link, bus_base,
reg, config_map);
printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
dst_node, dst_link, bus_base,
reg, config_map);
#endif
if ((dst_node == node) && (dst_link == link))
{
return bus_base;
}
}
return 0;
if ((dst_node == node) && (dst_link == link))
{
return bus_base;
}
}
return 0;
}
#endif
@ -87,8 +87,8 @@ unsigned node_link_to_bus(unsigned node, unsigned link)
* So we need to make sure that the south bridge link will always be on
* pci1234[0].
*
* Imagine a scenario with multiple HT I/O cards, where you don't install HT I/O 1,
* but you only install HT I/O 2 and HT I/O 3. The HT I/Os will end up in registers
* Imagine a scenario with multiple HT I/O cards, where you don't install HT I/O 1,
* but you only install HT I/O 2 and HT I/O 3. The HT I/Os will end up in registers
* 0xE4 and 0xE8.
*
* But we want to leave pci1234[1] to HT I/O 1 (even though it is disabled),
@ -119,7 +119,7 @@ unsigned node_link_to_bus(unsigned node, unsigned link)
* };
*
*
* For 4p+htio(n1)+htio(n2)+htio(n3),4p+htio(n1)+4p+htio(n6)+htio(n7):
* For 4p+htio(n1)+htio(n2)+htio(n3),4p+htio(n1)+4p+htio(n6)+htio(n7):
* You need an array pci1234[6]:
*
* unsigned pci1234[] = {
@ -130,10 +130,10 @@ unsigned node_link_to_bus(unsigned node, unsigned link)
* 0x0000f60, // HT IO 4 card always on node 6
* 0x0000f70 // HT IO 5 card always on node 7
* };
*
*
* For 2p + htio(n1) + htio(n0_1) + htio(n1_1), 2P + htio(n1) + 2P +
* htio(n2) + htio(n3), 2P + htio(n1) + 4P + htio(n4) + htio(n5),
*
*
* For 2p + htio(n1) + htio(n0_1) + htio(n1_1), 2P + htio(n1) + 2P +
* htio(n2) + htio(n3), 2P + htio(n1) + 4P + htio(n4) + htio(n5),
* you need an array pci1234[8]:
*
* unsigned pci1234[] = {
@ -146,10 +146,10 @@ unsigned node_link_to_bus(unsigned node, unsigned link)
* 0x0000f40, // HT IO 6 card always on node 4
* 0x0000f50 // HT IO 7 card always on node 5
* };
*
*
*
*
* For 4P + htio(n1) + htio(n2) + htio(n3), 4p + htio(n1) + 2p + htio(n4) +
* htio(n5), 4p + htio(n1) + 4p + htio(n6) + htio(n7),
* htio(n5), 4p + htio(n1) + 4p + htio(n6) + htio(n7),
* you need an array pci1234[8]:
*
* unsigned pci1234[] = {
@ -162,53 +162,53 @@ unsigned node_link_to_bus(unsigned node, unsigned link)
* 0x0000f60, // HT IO 6 card always on node 6
* 0x0000f70 // HT IO 7 card always on node 7
* };
*
*
*
*
* So the maximum posible value of HC_POSSIBLE_NUM is 8. (FIXME Why?)
*
*
* 1n: 3
* 2n: 2x2 - 1
* 4n: 1x4 - 2
* 6n: 2
* 8n: 2
* Total: 12
*
* Just put all the possible HT Node/link to the list tp pci1234[] in
* 4n: 1x4 - 2
* 6n: 2
* 8n: 2
* Total: 12
*
* Just put all the possible HT Node/link to the list tp pci1234[] in
* src/mainboard/<vendor>/<mainboard>get_bus_conf.c
*
*
* Also don't forget to increase the ACPI_SSDTX_NUM etc (FIXME what else) if
* you have too many SSDTs
*
*
* What about co-processor in socket 1 on a 2 way system? Or socket 2 and
* socket 3 on a 4 way system? Treat that as an HC, too!
*
*
*/
void get_sblk_pci1234(void)
{
device_t dev;
int i,j;
uint32_t dword;
device_t dev;
int i,j;
uint32_t dword;
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
dword = pci_read_config32(dev, 0x64);
sysconf.sblk = (dword>>8) & 0x3;
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
dword = pci_read_config32(dev, 0x64);
sysconf.sblk = (dword>>8) & 0x3;
dword &=0x0300;
dword |= 1;
sysconf.pci1234[0] = dword;
dword &=0x0300;
dword |= 1;
sysconf.pci1234[0] = dword;
sysconf.hcid[0] = 0;
/* About hardcoded numbering for HT_IO support
/* About hardcoded numbering for HT_IO support
*
* Set the node_id and link_id that could have a HT chain in the one
* array, (FIXME: which one?) then check if is enabled. Then update
* final value
*/
* final value
*/
/* Here we need to set hcdn
/* Here we need to set hcdn
*
* 1. hypertransport.c needs to record hcdn_reg together with 0xe0,
* 0xe4, 0xe8, 0xec when are set (FIXME: when WHAT is set?)
@ -216,48 +216,48 @@ void get_sblk_pci1234(void)
* 2. So at the same time we need update hcdn with hcdn_reg here. FIXME: Why?
*/
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
for(j=0;j<4;j++) {
uint32_t dwordx;
dwordx = pci_read_config32(dev, 0xe0 + j*4);
dwordx &=0xffff0ff1; /* keep bus num, node_id, link_num, enable bits */
if((dwordx & 0xff1) == dword) { /* SBLINK */
sysconf.pci1234[0] = dwordx;
for(j=0;j<4;j++) {
uint32_t dwordx;
dwordx = pci_read_config32(dev, 0xe0 + j*4);
dwordx &=0xffff0ff1; /* keep bus num, node_id, link_num, enable bits */
if((dwordx & 0xff1) == dword) { /* SBLINK */
sysconf.pci1234[0] = dwordx;
sysconf.hcdn[0] = sysconf.hcdn_reg[j];
continue;
}
continue;
}
if((dwordx & 1) == 1) {
/* We need to find out the number of HC
* for exact match
if((dwordx & 1) == 1) {
/* We need to find out the number of HC
* for exact match
*/
for(i=1;i<sysconf.hc_possible_num;i++) {
if((dwordx & 0xff0) == (sysconf.pci1234[i] & 0xff0)) {
sysconf.pci1234[i] = dwordx;
for(i=1;i<sysconf.hc_possible_num;i++) {
if((dwordx & 0xff0) == (sysconf.pci1234[i] & 0xff0)) {
sysconf.pci1234[i] = dwordx;
sysconf.hcdn[i] = sysconf.hcdn_reg[j];
break;
}
}
break;
}
}
/* For 0xff0 match or same node */
for(i=1;i<sysconf.hc_possible_num;i++) {
if((dwordx & 0xff0) == (dwordx & sysconf.pci1234[i] & 0xff0)) {
sysconf.pci1234[i] = dwordx;
/* For 0xff0 match or same node */
for(i=1;i<sysconf.hc_possible_num;i++) {
if((dwordx & 0xff0) == (dwordx & sysconf.pci1234[i] & 0xff0)) {
sysconf.pci1234[i] = dwordx;
sysconf.hcdn[i] = sysconf.hcdn_reg[j];
break;
}
}
}
}
break;
}
}
}
}
for(i=1;i<sysconf.hc_possible_num;i++) {
if((sysconf.pci1234[i] & 1) != 1) {
sysconf.pci1234[i] = 0;
for(i=1;i<sysconf.hc_possible_num;i++) {
if((sysconf.pci1234[i] & 1) != 1) {
sysconf.pci1234[i] = 0;
sysconf.hcdn[i] = 0x20202020;
}
}
sysconf.hcid[i] = 0;
}
}
}

565
src/northbridge/amd/amdk8/incoherent_ht.c
View File

@ -8,7 +8,7 @@
#include <device/hypertransport_def.h>
#ifndef K8_HT_FREQ_1G_SUPPORT
#define K8_HT_FREQ_1G_SUPPORT 0
#define K8_HT_FREQ_1G_SUPPORT 0
#endif
#ifndef K8_SCAN_PCI_BUS
@ -16,20 +16,20 @@
#endif
#ifndef K8_ALLOCATE_IO_RANGE
#define K8_ALLOCATE_IO_RANGE 0
#define K8_ALLOCATE_IO_RANGE 0
#endif
// Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM
// Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM
#ifndef K8_ALLOCATE_MMIO_RANGE
#define K8_ALLOCATE_MMIO_RANGE 0
#define K8_ALLOCATE_MMIO_RANGE 0
#endif
static inline void print_linkn_in (const char *strval, uint8_t byteval)
{
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%s%02x\r\n", strval, byteval);
printk_debug("%s%02x\r\n", strval, byteval);
#else
print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
#endif
}
@ -67,13 +67,13 @@ static uint8_t ht_lookup_capability(device_t dev, uint16_t val)
}
static uint8_t ht_lookup_slave_capability(device_t dev)
{
{
return ht_lookup_capability(dev, 0); // Slave/Primary Interface Block Format
}
static uint8_t ht_lookup_host_capability(device_t dev)
{
return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format
return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format
}
static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid)
@ -91,12 +91,12 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid
/* Check if is already collapsed */
if((!offset_unitid) || (offset_unitid && (!((HT_CHAIN_END_UNITID_BASE == 0) && (HT_CHAIN_END_UNITID_BASE <HT_CHAIN_UNITID_BASE))))) {
dev = PCI_DEV(bus, 0, 0);
id = pci_read_config32(dev, PCI_VENDOR_ID);
if ( ! ( (id == 0xffffffff) || (id == 0x00000000) ||
(id == 0x0000ffff) || (id == 0xffff0000) ) ) {
return;
}
}
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (!((id == 0xffffffff) || (id == 0x00000000) ||
(id == 0x0000ffff) || (id == 0xffff0000))) {
return;
}
}
/* Spin through the devices and collapse any previous
* hypertransport enumeration.
@ -105,13 +105,13 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid
uint32_t id;
uint8_t pos;
uint16_t flags;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if ((id == 0xffffffff) || (id == 0x00000000) ||
(id == 0x0000ffff) || (id == 0xffff0000)) {
continue;
}
pos = ht_lookup_slave_capability(dev);
if (!pos) {
continue;
@ -145,23 +145,24 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos)
if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8151_SYSCTRL << 16))) {
freq_cap &= ~(1 << HT_FREQ_800Mhz);
return freq_cap;
}
}
/* AMD K8 Unsupported 1Ghz? */
if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
#if K8_HT_FREQ_1G_SUPPORT == 1
#if K8_REV_F_SUPPORT == 0
if (is_cpu_pre_e0()) { // only E0 later support 1GHz
#if K8_HT_FREQ_1G_SUPPORT == 1
#if K8_REV_F_SUPPORT == 0
if (is_cpu_pre_e0()) { // only E0 later support 1GHz
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
}
#endif
#else
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
#else
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
#endif
}
return freq_cap;
}
static uint8_t ht_read_width_cap(device_t dev, uint8_t pos)
{
uint8_t width_cap = pci_read_config8(dev, pos);
@ -176,12 +177,13 @@ static uint8_t ht_read_width_cap(device_t dev, uint8_t pos)
width_cap &= 0x88;
}
}
return width_cap;
}
#define LINK_OFFS(CTRL, WIDTH,FREQ,FREQ_CAP) \
(((CTRL & 0xff) << 24) | ((WIDTH & 0xff) << 16) | ((FREQ & 0xff) << 8) | (FREQ_CAP & 0xFF))
(((CTRL & 0xff) << 24) | ((WIDTH & 0xff) << 16) | ((FREQ & 0xff) << 8) | (FREQ_CAP & 0xFF))
#define LINK_CTRL(OFFS) ((OFFS >> 24) & 0xFF)
#define LINK_WIDTH(OFFS) ((OFFS >> 16) & 0xFF)
@ -189,19 +191,19 @@ static uint8_t ht_read_width_cap(device_t dev, uint8_t pos)
#define LINK_FREQ_CAP(OFFS) ((OFFS) & 0xFF)
#define PCI_HT_HOST_OFFS LINK_OFFS( \
PCI_HT_CAP_HOST_CTRL, \
PCI_HT_CAP_HOST_CTRL, \
PCI_HT_CAP_HOST_WIDTH, \
PCI_HT_CAP_HOST_FREQ, \
PCI_HT_CAP_HOST_FREQ_CAP)
#define PCI_HT_SLAVE0_OFFS LINK_OFFS( \
PCI_HT_CAP_SLAVE_CTRL0, \
PCI_HT_CAP_SLAVE_CTRL0, \
PCI_HT_CAP_SLAVE_WIDTH0, \
PCI_HT_CAP_SLAVE_FREQ0, \
PCI_HT_CAP_SLAVE_FREQ_CAP0)
#define PCI_HT_SLAVE1_OFFS LINK_OFFS( \
PCI_HT_CAP_SLAVE_CTRL1, \
PCI_HT_CAP_SLAVE_CTRL1, \
PCI_HT_CAP_SLAVE_WIDTH1, \
PCI_HT_CAP_SLAVE_FREQ1, \
PCI_HT_CAP_SLAVE_FREQ_CAP1)
@ -280,22 +282,23 @@ static int ht_optimize_link(
return needs_reset;
}
#if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1)
#if RAMINIT_SYSINFO == 1
static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo);
static int scan_pci_bus( unsigned bus , struct sys_info *sysinfo)
static int scan_pci_bus( unsigned bus , struct sys_info *sysinfo)
#else
static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid);
static int scan_pci_bus( unsigned bus)
#endif
{
/*
here we already can access PCI_DEV(bus, 0, 0) to PCI_DEV(bus, 0x1f, 0x7)
So We can scan these devices to find out if they are bridge
If it is pci bridge, We need to set busn in bridge, and go on
For ht bridge, We need to set the busn in bridge and ht_setup_chainx, and the scan_pci_bus
*/
/*
here we already can access PCI_DEV(bus, 0, 0) to PCI_DEV(bus, 0x1f, 0x7)
So We can scan these devices to find out if they are bridge
If it is pci bridge, We need to set busn in bridge, and go on
For ht bridge, We need to set the busn in bridge and ht_setup_chainx, and the scan_pci_bus
*/
unsigned int devfn;
unsigned new_bus;
unsigned max_bus;
@ -314,85 +317,85 @@ static int scan_pci_bus( unsigned bus)
new_bus = bus;
for (devfn = 0; devfn <= 0xff; devfn++) {
uint8_t hdr_type;
uint16_t class;
for (devfn = 0; devfn <= 0xff; devfn++) {
uint8_t hdr_type;
uint16_t class;
uint32_t buses;
device_t dev;
uint16_t cr;
dev = PCI_DEV((bus & 0xff), ((devfn>>3) & 0x1f), (devfn & 0x7));
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
class = pci_read_config16(dev, PCI_CLASS_DEVICE);
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
class = pci_read_config16(dev, PCI_CLASS_DEVICE);
switch(hdr_type & 0x7f) { /* header type */
case PCI_HEADER_TYPE_BRIDGE:
if (class != PCI_CLASS_BRIDGE_PCI) goto bad;
case PCI_HEADER_TYPE_BRIDGE:
if (class != PCI_CLASS_BRIDGE_PCI) goto bad;
/* set the bus range dev */
/* Clear all status bits and turn off memory, I/O and master enables. */
cr = pci_read_config16(dev, PCI_COMMAND);
pci_write_config16(dev, PCI_COMMAND, 0x0000);
pci_write_config16(dev, PCI_STATUS, 0xffff);
/* Clear all status bits and turn off memory, I/O and master enables. */
cr = pci_read_config16(dev, PCI_COMMAND);
pci_write_config16(dev, PCI_COMMAND, 0x0000);
pci_write_config16(dev, PCI_STATUS, 0xffff);
buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
buses &= 0xff000000;
buses &= 0xff000000;
new_bus++;
buses |= (((unsigned int) (bus & 0xff) << 0) |
((unsigned int) (new_bus & 0xff) << 8) |
((unsigned int) max_bus << 16));
pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
buses |= (((unsigned int) (bus & 0xff) << 0) |
((unsigned int) (new_bus & 0xff) << 8) |
((unsigned int) max_bus << 16));
pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
/* here we need to figure out if dev is a ht bridge
if it is ht bridge, we need to call ht_setup_chainx at first
Not verified --- yhlu
Not verified --- yhlu
*/
uint8_t upos;
upos = ht_lookup_host_capability(dev); // one func one ht sub
if (upos) { // sub ht chain
upos = ht_lookup_host_capability(dev); // one func one ht sub
if (upos) { // sub ht chain
uint8_t busn;
busn = (new_bus & 0xff);
/* Make certain the HT bus is not enumerated */
ht_collapse_previous_enumeration(busn, 0);
/* Make certain the HT bus is not enumerated */
ht_collapse_previous_enumeration(busn, 0);
/* scan the ht chain */
#if RAMINIT_SYSINFO == 1
ht_setup_chainx(dev,upos,busn, 0, sysinfo); // don't need offset unitid
ht_setup_chainx(dev,upos,busn, 0, sysinfo); // don't need offset unitid
#else
new_bus |= (ht_setup_chainx(dev, upos, busn, 0)<<16); // store reset_needed to upword
#endif
}
#if RAMINIT_SYSINFO == 1
}
#if RAMINIT_SYSINFO == 1
new_bus = scan_pci_bus(new_bus, sysinfo);
#else
new_bus = scan_pci_bus(new_bus);
#endif
/* set real max bus num in that */
buses = (buses & 0xff00ffff) |
((unsigned int) (new_bus & 0xff) << 16);
pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
buses = (buses & 0xff00ffff) |
((unsigned int) (new_bus & 0xff) << 16);
pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
pci_write_config16(dev, PCI_COMMAND, cr);
break;
default:
bad:
break;
default:
bad:
;
}
}
/* if this is not a multi function device,
* or the device is not present don't waste
* time probing another function.
* Skip to next device.
*/
if ( ((devfn & 0x07) == 0x00) && ((hdr_type & 0x80) != 0x80))
{
devfn += 0x07;
}
}
return new_bus;
/* if this is not a multi function device,
* or the device is not present don't waste
* time probing another function.
* Skip to next device.
*/
if ( ((devfn & 0x07) == 0x00) && ((hdr_type & 0x80) != 0x80))
{
devfn += 0x07;
}
}
return new_bus;
}
#endif
@ -412,9 +415,9 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
#endif
#if HT_CHAIN_END_UNITID_BASE != 0x20
//let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE
unsigned real_last_unitid;
uint8_t real_last_pos;
//let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE
unsigned real_last_unitid;
uint8_t real_last_pos;
int ht_dev_num = 0;
uint8_t end_used = 0;
#endif
@ -428,50 +431,50 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
uint16_t flags, ctrl;
uint8_t count;
unsigned offs;
/* Wait until the link initialization is complete */
do {
ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs));
/* Is this the end of the hypertransport chain? */
if (ctrl & (1 << 6)) {
goto end_of_chain;
goto end_of_chain;
}
if (ctrl & ((1 << 4) | (1 << 8))) {
/*
* Either the link has failed, or we have
* a CRC error.
* Sometimes this can happen due to link
* retrain, so lets knock it down and see
* if its transient
*/
/*
* Either the link has failed, or we have
* a CRC error.
* Sometimes this can happen due to link
* retrain, so lets knock it down and see
* if its transient
*/
ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
pci_write_config16(udev, upos + LINK_CTRL(uoffs), ctrl);
ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs));
if (ctrl & ((1 << 4) | (1 << 8))) {
print_err("Detected error on Hypertransport Link\n");
pci_write_config16(udev, upos + LINK_CTRL(uoffs), ctrl);
ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs));
if (ctrl & ((1 << 4) | (1 << 8))) {
print_err("Detected error on Hypertransport Link\n");
break;
}
}
}
} while((ctrl & (1 << 5)) == 0);
device_t dev = PCI_DEV(bus, 0, 0);
last_unitid = next_unitid;
id = pci_read_config32(dev, PCI_VENDOR_ID);
/* If the chain is enumerated quit */
if ( (id == 0xffffffff) || (id == 0x00000000) ||
(id == 0x0000ffff) || (id == 0xffff0000))
if ((id == 0xffffffff) || (id == 0x00000000) ||
(id == 0x0000ffff) || (id == 0xffff0000))
{
break;
}
pos = ht_lookup_slave_capability(dev);
if (!pos) {
print_err("udev="); print_err_hex32(udev);
print_err("\tupos="); print_err_hex32(upos);
print_err("\tuoffs="); print_err_hex32(uoffs);
print_err("udev="); print_err_hex32(udev);
print_err("\tupos="); print_err_hex32(upos);
print_err("\tuoffs="); print_err_hex32(uoffs);
print_err("\tHT link capability not found\r\n");
break;
}
@ -481,17 +484,17 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
if(offset_unitid) {
if(next_unitid>= (bus ? 0x20:0x18) ) {
if(!end_used) {
next_unitid = HT_CHAIN_END_UNITID_BASE;
next_unitid = HT_CHAIN_END_UNITID_BASE;
end_used = 1;
} else {
goto out;
}
}
real_last_pos = pos;
}
real_last_pos = pos;
real_last_unitid = next_unitid;
ht_dev_num++;
}
}
#endif
/* Update the Unitid of the current device */
flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
@ -499,23 +502,23 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
flags |= next_unitid & 0x1f;
pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
/* Compute the number of unitids consumed */
count = (flags >> 5) & 0x1f;
/* Compute the number of unitids consumed */
count = (flags >> 5) & 0x1f;
/* Note the change in device number */
dev = PCI_DEV(bus, next_unitid, 0);
next_unitid += count;
next_unitid += count;
/* Find which side of the ht link we are on,
* by reading which direction our last write to PCI_CAP_FLAGS
* came from.
*/
flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;
offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;
#if RAMINIT_SYSINFO == 1
/* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */
/* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */
{
struct link_pair_st *link_pair = &sysinfo->link_pair[sysinfo->link_pair_num];
link_pair->udev = udev;
@ -539,32 +542,32 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
out:
end_of_chain: ;
#if HT_CHAIN_END_UNITID_BASE != 0x20
if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used ) {
uint16_t flags;
int i;
flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
flags &= ~0x1f;
flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
#if RAMINIT_SYSINFO == 1
#if HT_CHAIN_END_UNITID_BASE != 0x20
if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used ) {
uint16_t flags;
int i;
flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
flags &= ~0x1f;
flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
#if RAMINIT_SYSINFO == 1
// Here need to change the dev in the array
for(i=0;i<sysinfo->link_pair_num;i++)
{
struct link_pair_st *link_pair = &sysinfo->link_pair[i];
if(link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) {
{
struct link_pair_st *link_pair = &sysinfo->link_pair[i];
if(link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) {
link_pair->udev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0);
continue;
}
if(link_pair->dev == PCI_DEV(bus, real_last_unitid, 0)) {
link_pair->dev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0);
}
}
if(link_pair->dev == PCI_DEV(bus, real_last_unitid, 0)) {
link_pair->dev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0);
}
}
#endif
}
}
#endif
#if RAMINIT_SYSINFO == 0
@ -581,55 +584,55 @@ static int ht_setup_chain(device_t udev, unsigned upos)
{
unsigned offset_unitid = 0;
#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
offset_unitid = 1;
offset_unitid = 1;
#endif
/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
* On most boards this just happens. If a cpu has multiple
* non Coherent links the appropriate bus registers for the
* links needs to be programed to point at bus 0.
*/
/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
* On most boards this just happens. If a cpu has multiple
* non Coherent links the appropriate bus registers for the
* links needs to be programed to point at bus 0.
*/
/* Make certain the HT bus is not enumerated */
ht_collapse_previous_enumeration(0, 0);
/* Make certain the HT bus is not enumerated */
ht_collapse_previous_enumeration(0, 0);
#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
offset_unitid = 1;
offset_unitid = 1;
#endif
#if RAMINIT_SYSINFO == 1
ht_setup_chainx(udev, upos, 0, offset_unitid, sysinfo);
#else
return ht_setup_chainx(udev, upos, 0, offset_unitid);
return ht_setup_chainx(udev, upos, 0, offset_unitid);
#endif
}
static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt, uint8_t val)
{
uint32_t dword, dword_old;
uint8_t link_type;
/* This works on an Athlon64 because unimplemented links return 0 */
dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x98 + (linkn * 0x20));
link_type = dword & 0xff;
if ( (link_type & 7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,3), 0xdc);
dword &= ~( 0xff<<(linkn *8) );
dword |= val << (linkn *8);
if (dword != dword_old) {
pci_write_config32(PCI_DEV(0,0x18+node,3), 0xdc, dword);
return 1;
}
}
return 0;
}
static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
{
int reset_needed;
int reset_needed;
uint8_t i;
reset_needed = 0;
@ -642,14 +645,14 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
unsigned devn = 1;
#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
if(i==0) // to check if it is sb ht chain
#endif
devn = HT_CHAIN_UNITID_BASE;
#endif
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
if(i==0) // to check if it is sb ht chain
#endif
devn = HT_CHAIN_UNITID_BASE;
#endif
reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
nodeid = ((reg & 0xf0)>>4); // nodeid
linkn = ((reg & 0xf00)>>8); // link n
busn = (reg & 0xff0000)>>16; //busn
@ -672,59 +675,59 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)
{
uint32_t dword;
uint8_t link_type;
uint32_t dword;
uint8_t link_type;
unsigned regpos;
device_t dev;
/* This works on an Athlon64 because unimplemented links return 0 */
/* This works on an Athlon64 because unimplemented links return 0 */
regpos = 0x98 + (linkn * 0x20);
dev = PCI_DEV(0,0x18+node,0);
dword = pci_read_config32(dev, regpos);
link_type = dword & 0xff;
dword = pci_read_config32(dev, regpos);
link_type = dword & 0xff;
if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
regpos = 0x90 + (linkn * 0x20);
dword = pci_read_config32(dev, regpos );
dword = pci_read_config32(dev, regpos );
if (dword != val) {
pci_write_config32(dev, regpos, val);
return 1;
}
if (dword != val) {
pci_write_config32(dev, regpos, val);
return 1;
}
}
return 0;
return 0;
}
static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val)
{
int reset_needed;
uint8_t i;
int reset_needed;
uint8_t i;
reset_needed = 0;
reset_needed = 0;
for (i = 0; i < ht_c_num; i++) {
uint32_t reg;
uint8_t nodeid, linkn;
uint8_t busn;
unsigned devn;
for (i = 0; i < ht_c_num; i++) {
uint32_t reg;
uint8_t nodeid, linkn;
uint8_t busn;
unsigned devn;
reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
if((reg & 3) != 3) continue; // not enabled
reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
if((reg & 3) != 3) continue; // not enabled
nodeid = ((reg & 0xf0)>>4); // nodeid
linkn = ((reg & 0xf00)>>8); // link n
busn = (reg & 0xff0000)>>16; //busn
nodeid = ((reg & 0xf0)>>4); // nodeid
linkn = ((reg & 0xf00)>>8); // link n
busn = (reg & 0xff0000)>>16; //busn
for(devn = 0; devn < 0x20; devn++) {
reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1?
if ( (reg & 0xffff) == vendorid ) {
reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1?
if ( (reg & 0xffff) == vendorid ) {
reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
break;
}
}
}
}
}
return reset_needed;
return reset_needed;
}
@ -734,13 +737,13 @@ static void ht_setup_chains(uint8_t ht_c_num, struct sys_info *sysinfo)
static int ht_setup_chains(uint8_t ht_c_num)
#endif
{
/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
* On most boards this just happens. If a cpu has multiple
* non Coherent links the appropriate bus registers for the
* links needs to be programed to point at bus 0.
*/
uint8_t upos;
device_t udev;
uint8_t upos;
device_t udev;
uint8_t i;
#if RAMINIT_SYSINFO == 0
@ -760,29 +763,29 @@ static int ht_setup_chains(uint8_t ht_c_num)
unsigned bus;
#endif
unsigned offset_unitid = 0;
reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
//We need setup 0x94, 0xb4, and 0xd4 according to the reg
devpos = ((reg & 0xf0)>>4)+0x18; // nodeid; it will decide 0x18 or 0x19
regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n; it will decide 0x94 or 0xb4, 0x0xd4;
busn = (reg & 0xff0000)>>16;
dword = pci_read_config32( PCI_DEV(0, devpos, 0), regpos) ;
dword &= ~(0xffff<<8);
dword |= (reg & 0xffff0000)>>8;
pci_write_config32( PCI_DEV(0, devpos,0), regpos , dword);
#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
if(i==0) // to check if it is sb ht chain
#endif
offset_unitid = 1;
#endif
/* Make certain the HT bus is not enumerated */
ht_collapse_previous_enumeration(busn, offset_unitid);
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
if(i==0) // to check if it is sb ht chain
#endif
offset_unitid = 1;
#endif
/* Make certain the HT bus is not enumerated */
ht_collapse_previous_enumeration(busn, offset_unitid);
upos = ((reg & 0xf00)>>8) * 0x20 + 0x80;
udev = PCI_DEV(0, devpos, 0);
@ -794,10 +797,10 @@ static int ht_setup_chains(uint8_t ht_c_num)
#endif
#if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1)
/* You can use use this in romcc, because there is function call in romcc, recursive will kill you */
bus = busn; // we need 32 bit
/* You can use use this in romcc, because there is function call in romcc, recursive will kill you */
bus = busn; // we need 32 bit
#if RAMINIT_SYSINFO == 1
scan_pci_bus(bus, sysinfo);
scan_pci_bus(bus, sysinfo);
#else
reset_needed |= (scan_pci_bus(bus)>>16); // take out reset_needed that stored in upword
#endif
@ -821,30 +824,30 @@ static void ht_setup_chains_x(struct sys_info *sysinfo)
#else
static int ht_setup_chains_x(void)
#endif
{
uint8_t nodeid;
uint32_t reg;
{
uint8_t nodeid;
uint32_t reg;
uint32_t tempreg;
uint8_t next_busn;
uint8_t ht_c_num;
uint8_t next_busn;
uint8_t ht_c_num;
uint8_t nodes;
#if K8_ALLOCATE_IO_RANGE == 1
#if K8_ALLOCATE_IO_RANGE == 1
unsigned next_io_base;
#endif
nodes = get_nodes();
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
/* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */
nodes = get_nodes();
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
/* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */
print_linkn_in("SBLink=", ((reg>>8) & 3) );
#if RAMINIT_SYSINFO == 1
sysinfo->sblk = (reg>>8) & 3;
sysinfo->sbbusn = 0;
sysinfo->nodes = nodes;
#endif
tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg);
tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg);
next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/
@ -858,95 +861,95 @@ static int ht_setup_chains_x(void)
#endif
/* clean others */
for(ht_c_num=1;ht_c_num<4; ht_c_num++) {
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
for(ht_c_num=1;ht_c_num<4; ht_c_num++) {
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
#if K8_ALLOCATE_IO_RANGE == 1
/* io range allocation */
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0);
#endif
}
for(nodeid=0; nodeid<nodes; nodeid++) {
device_t dev;
uint8_t linkn;
dev = PCI_DEV(0, 0x18+nodeid,0);
for(linkn = 0; linkn<3; linkn++) {
unsigned regpos;
regpos = 0x98 + 0x20 * linkn;
reg = pci_read_config32(dev, regpos);
if ((reg & 0x17) != 7) continue; /* it is not non conherent or not connected*/
}
for(nodeid=0; nodeid<nodes; nodeid++) {
device_t dev;
uint8_t linkn;
dev = PCI_DEV(0, 0x18+nodeid,0);
for(linkn = 0; linkn<3; linkn++) {
unsigned regpos;
regpos = 0x98 + 0x20 * linkn;
reg = pci_read_config32(dev, regpos);
if ((reg & 0x17) != 7) continue; /* it is not non conherent or not connected*/
print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf));
tempreg = 3 | (nodeid <<4) | (linkn<<8);
/*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */
for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
if(((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/
break;
}
}
if(ht_c_num == 4) break; /*used up only 4 non conherent allowed*/
/*update to 0xe0...*/
tempreg = 3 | (nodeid <<4) | (linkn<<8);
/*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */
for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
if(((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/
break;
}
}
if(ht_c_num == 4) break; /*used up only 4 non conherent allowed*/
/*update to 0xe0...*/
if((reg & 0xf) == 3) continue; /*SbLink so don't touch it */
print_linkn_in("\tbusn=", next_busn);
tempreg |= (next_busn<<16)|((next_busn+0x3f)<<24);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);
tempreg |= (next_busn<<16)|((next_busn+0x3f)<<24);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);
next_busn+=0x3f+1;
#if K8_ALLOCATE_IO_RANGE == 1
#if K8_ALLOCATE_IO_RANGE == 1
/* io range allocation */
tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);
tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ?
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg);
next_io_base += 0x3+0x1;
tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);
tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ?
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg);
next_io_base += 0x3+0x1;
#endif
}
}
/*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/
}
}
/*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/
for(nodeid = 1; nodeid<nodes; nodeid++) {
int i;
device_t dev;
dev = PCI_DEV(0, 0x18+nodeid,1);
for(i = 0; i< 4; i++) {
unsigned regpos;
regpos = 0xe0 + i * 4;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
pci_write_config32(dev, regpos, reg);
}
for(nodeid = 1; nodeid<nodes; nodeid++) {
int i;
device_t dev;
dev = PCI_DEV(0, 0x18+nodeid,1);
for(i = 0; i< 4; i++) {
unsigned regpos;
regpos = 0xe0 + i * 4;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
pci_write_config32(dev, regpos, reg);
}
#if K8_ALLOCATE_IO_RANGE == 1
/* io range allocation */
for(i = 0; i< 4; i++) {
unsigned regpos;
regpos = 0xc4 + i * 8;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
pci_write_config32(dev, regpos, reg);
}
for(i = 0; i< 4; i++) {
unsigned regpos;
regpos = 0xc0 + i * 8;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
pci_write_config32(dev, regpos, reg);
}
for(i = 0; i< 4; i++) {
unsigned regpos;
regpos = 0xc4 + i * 8;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
pci_write_config32(dev, regpos, reg);
}
for(i = 0; i< 4; i++) {
unsigned regpos;
regpos = 0xc0 + i * 8;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
pci_write_config32(dev, regpos, reg);
}
#endif
}
}
/* recount ht_c_num*/
uint8_t i=0;
for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
if(((reg & 0xf) != 0x0)) {
if(((reg & 0xf) != 0x0)) {
i++;
}
}
}
#if RAMINIT_SYSINFO == 1
sysinfo->ht_c_num = i;
ht_setup_chains(i, sysinfo);
ht_setup_chains(i, sysinfo);
sysinfo->sbdn = get_sbdn(sysinfo->sbbusn);
#else
return ht_setup_chains(i);
@ -960,10 +963,10 @@ static int optimize_link_incoherent_ht(struct sys_info *sysinfo)
// We need to use recorded link pair info to optimize the link
int i;
int reset_needed = 0;
unsigned link_pair_num = sysinfo->link_pair_num;
for(i=0; i< link_pair_num; i++) {
for(i=0; i< link_pair_num; i++) {
struct link_pair_st *link_pair= &sysinfo->link_pair[i];
reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs);
}

576
src/northbridge/amd/amdk8/northbridge.c
View File

@ -103,14 +103,14 @@ static unsigned int amdk8_nodeid(device_t dev)
static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid)
{
uint32_t link_type;
int i;
uint32_t busses, config_busses;
unsigned free_reg, config_reg;
unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain
unsigned max_bus;
unsigned min_bus;
unsigned max_bus;
unsigned min_bus;
unsigned max_devfn;
dev->link[link].cap = 0x80 + (link *0x20);
@ -127,7 +127,7 @@ static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned lin
return max;
}
/* See if there is an available configuration space mapping
* register in function 1.
* register in function 1.
*/
free_reg = 0;
for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
@ -137,7 +137,7 @@ static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned lin
free_reg = config_reg;
continue;
}
if (((config & 3) == 3) &&
if (((config & 3) == 3) &&
(((config >> 4) & 7) == nodeid) &&
(((config >> 8) & 3) == link)) {
break;
@ -147,7 +147,7 @@ static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned lin
config_reg = free_reg;
}
/* If we can't find an available configuration space mapping
* register skip this bus
* register skip this bus
*/
if (config_reg > 0xec) {
return max;
@ -158,36 +158,36 @@ static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned lin
* so we set the subordinate bus number to 0xff for the moment.
*/
#if SB_HT_CHAIN_ON_BUS0 > 0
// first chain will on bus 0
// first chain will on bus 0
if((nodeid == 0) && (sblink==link)) { // actually max is 0 here
min_bus = max;
}
min_bus = max;
}
#if SB_HT_CHAIN_ON_BUS0 > 1
// second chain will be on 0x40, third 0x80, forth 0xc0
else {
min_bus = ((max>>6) + 1) * 0x40;
}
max = min_bus;
#else
//other ...
else {
min_bus = ++max;
}
#endif
else {
min_bus = ((max>>6) + 1) * 0x40;
}
max = min_bus;
#else
//other ...
else {
min_bus = ++max;
}
#endif
#else
min_bus = ++max;
min_bus = ++max;
#endif
max_bus = 0xff;
max_bus = 0xff;
dev->link[link].secondary = min_bus;
dev->link[link].subordinate = max_bus;
dev->link[link].secondary = min_bus;
dev->link[link].subordinate = max_bus;
/* Read the existing primary/secondary/subordinate bus
* number configuration.
*/
busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
config_busses = f1_read_config32(config_reg);
/* Configure the bus numbers for this bridge: the configuration
* transactions will not be propagates by the bridge if it is
* not correctly configured
@ -199,22 +199,22 @@ static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned lin
pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
config_busses &= 0x000fc88;
config_busses |=
config_busses |=
(3 << 0) | /* rw enable, no device compare */
(( nodeid & 7) << 4) |
(( link & 3 ) << 8) |
(( nodeid & 7) << 4) |
(( link & 3 ) << 8) |
((dev->link[link].secondary) << 16) |
((dev->link[link].subordinate) << 24);
f1_write_config32(config_reg, config_busses);
/* Now we can scan all of the subordinate busses i.e. the
* chain on the hypertranport link
* chain on the hypertranport link
*/
for(i=0;i<4;i++) {
ht_unitid_base[i] = 0x20;
}
if (min_bus == 0)
if (min_bus == 0)
max_devfn = (0x17<<3) | 7;
else
max_devfn = (0x1f<<3) | 7;
@ -251,42 +251,42 @@ static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned lin
static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
{
unsigned nodeid;
unsigned link;
unsigned sblink = 0;
unsigned nodeid;
unsigned link;
unsigned sblink = 0;
unsigned offset_unitid = 0;
nodeid = amdk8_nodeid(dev);
if(nodeid==0) {
sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
nodeid = amdk8_nodeid(dev);
if(nodeid==0) {
sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
#if SB_HT_CHAIN_ON_BUS0 > 0
#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
offset_unitid = 1;
#endif
offset_unitid = 1;
#endif
max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
#endif
}
}
for(link = 0; link < dev->links; link++) {
for(link = 0; link < dev->links; link++) {
#if SB_HT_CHAIN_ON_BUS0 > 0
if( (nodeid == 0) && (sblink == link) ) continue; //already done
#endif
offset_unitid = 0;
#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
if((nodeid == 0) && (sblink == link))
#endif
offset_unitid = 1;
#endif
max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid);
}
}
return max;
return max;
}
static int reg_useable(unsigned reg,
static int reg_useable(unsigned reg,
device_t goal_dev, unsigned goal_nodeid, unsigned goal_link)
{
struct resource *res;
@ -303,7 +303,7 @@ static int reg_useable(unsigned reg,
result = 2;
if (res) {
result = 0;
if ( (goal_link == (link - 1)) &&
if ( (goal_link == (link - 1)) &&
(goal_nodeid == (nodeid - 1)) &&
(res->flags <= 1)) {
result = 1;
@ -370,7 +370,7 @@ static struct resource *amdk8_find_mempair(device_t dev, unsigned nodeid, unsign
static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
{
struct resource *resource;
/* Initialize the io space constraints on the current bus */
resource = amdk8_find_iopair(dev, nodeid, link);
if (resource) {
@ -380,7 +380,7 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
resource->gran = log2(HT_IO_HOST_ALIGN);
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
compute_allocate_resource(&dev->link[link], resource,
compute_allocate_resource(&dev->link[link], resource,
IORESOURCE_IO, IORESOURCE_IO);
}
@ -393,8 +393,8 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
compute_allocate_resource(&dev->link[link], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
compute_allocate_resource(&dev->link[link], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM | IORESOURCE_PREFETCH);
}
@ -407,8 +407,8 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM;
compute_allocate_resource(&dev->link[link], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
compute_allocate_resource(&dev->link[link], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM);
}
}
@ -439,7 +439,7 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
if (resource->flags & IORESOURCE_STORED) {
return;
}
/* Only handle PCI memory and IO resources */
if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
return;
@ -450,7 +450,7 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
}
/* Get the base address */
rbase = resource->base;
/* Get the limit (rounded up) */
rend = resource_end(resource);
@ -473,14 +473,14 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
limit |= (nodeid & 7);
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n",
__func__, dev_path(dev), link);
printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n",
__func__, dev_path(dev), link);
base |= PCI_IO_BASE_VGA_EN;
}
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
base |= PCI_IO_BASE_NO_ISA;
}
f1_write_config32(reg + 0x4, limit);
f1_write_config32(reg, base);
}
@ -513,7 +513,7 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
* but it is too diffcult to deal with the resource allocation magic.
*/
#if CONFIG_CONSOLE_VGA_MULTI == 1
extern device_t vga_pri; // the primary vga device, defined in device.c
extern device_t vga_pri; // the primary vga device, defined in device.c
#endif
static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
@ -528,7 +528,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
for (link = 0; link < dev->links; link++) {
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#if CONFIG_CONSOLE_VGA_MULTI == 1
printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
dev->link[link].secondary,dev->link[link].subordinate);
/* We need to make sure the vga_pri is under the link */
if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
@ -538,7 +538,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
break;
}
}
/* no VGA card installed */
if (link == dev->links)
return;
@ -581,7 +581,7 @@ static void amdk8_set_resources(device_t dev)
nodeid = amdk8_nodeid(dev);
amdk8_create_vga_resource(dev, nodeid);
/* Set each resource we have found */
for(i = 0; i < dev->resources; i++) {
amdk8_set_resource(dev, &dev->resource[i], nodeid);
@ -604,7 +604,7 @@ static void amdk8_enable_resources(device_t dev)
static void mcf0_control_init(struct device *dev)
{
#if 0
#if 0
printk_debug("NB: Function 0 Misc Control.. ");
#endif
#if 0
@ -673,38 +673,38 @@ static void pci_domain_read_resources(device_t dev)
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
#else
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0);
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_IO, IORESOURCE_IO);
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0);
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_IO, IORESOURCE_IO);
/* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 1);
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM | IORESOURCE_PREFETCH);
/* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 1);
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM | IORESOURCE_PREFETCH);
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 2);
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM);
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 2);
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM);
#endif
}
static void ram_resource(device_t dev, unsigned long index,
static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{
struct resource *resource;
@ -759,83 +759,83 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
struct hw_mem_hole_info mem_hole;
int i;
mem_hole.hole_startk = HW_MEM_HOLE_SIZEK;
mem_hole.hole_startk = HW_MEM_HOLE_SIZEK;
mem_hole.node_id = -1;
for (i = 0; i < 8; i++) {
uint32_t base;
uint32_t hole;
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
hole = pci_read_config32(__f1_dev[i], 0xf0);
if(hole & 1) { // we find the hole
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
mem_hole.node_id = i; // record the node No with hole
break; // only one hole
for (i = 0; i < 8; i++) {
uint32_t base;
uint32_t hole;
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
}
//We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
if(mem_hole.node_id==-1) {
uint32_t limitk_pri = 0;
for(i=0; i<8; i++) {
uint32_t base, limit;
unsigned base_k, limit_k;
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
hole = pci_read_config32(__f1_dev[i], 0xf0);
if(hole & 1) { // we find the hole
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
mem_hole.node_id = i; // record the node No with hole
break; // only one hole
}
}
base_k = (base & 0xffff0000) >> 2;
if(limitk_pri != base_k) { // we find the hole
mem_hole.hole_startk = limitk_pri;
mem_hole.node_id = i;
break; //only one hole
//We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
if(mem_hole.node_id==-1) {
uint32_t limitk_pri = 0;
for(i=0; i<8; i++) {
uint32_t base, limit;
unsigned base_k, limit_k;
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
limit = f1_read_config32(0x44 + (i << 3));
limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
limitk_pri = limit_k;
}
}
base_k = (base & 0xffff0000) >> 2;
if(limitk_pri != base_k) { // we find the hole
mem_hole.hole_startk = limitk_pri;
mem_hole.node_id = i;
break; //only one hole
}
limit = f1_read_config32(0x44 + (i << 3));
limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
limitk_pri = limit_k;
}
}
return mem_hole;
}
static void disable_hoist_memory(unsigned long hole_startk, int i)
{
int ii;
device_t dev;
uint32_t base, limit;
uint32_t hoist;
int ii;
device_t dev;
uint32_t base, limit;
uint32_t hoist;
uint32_t hole_sizek;
//1. find which node has hole
//2. change limit in that node.
//3. change base and limit in later node
//4. clear that node f0
//1. find which node has hole
//2. change limit in that node.
//3. change base and limit in later node
//4. clear that node f0
//if there is not mem hole enabled, we need to change it's base instead
hole_sizek = (4*1024*1024) - hole_startk;
for(ii=7;ii>i;ii--) {
for(ii=7;ii>i;ii--) {
base = f1_read_config32(0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
base = f1_read_config32(0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
limit = f1_read_config32(0x44 + (ii << 3));
f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
}
limit = f1_read_config32(0x44 + (i << 3));
f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
dev = __f1_dev[i];
f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
}
limit = f1_read_config32(0x44 + (i << 3));
f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
dev = __f1_dev[i];
hoist = pci_read_config32(dev, 0xf0);
if(hoist & 1) {
pci_write_config32(dev, 0xf0, 0);
@ -844,35 +844,35 @@ static void disable_hoist_memory(unsigned long hole_startk, int i)
base = pci_read_config32(dev, 0x40 + (i << 3));
f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
}
}
static uint32_t hoist_memory(unsigned long hole_startk, int i)
{
int ii;
uint32_t carry_over;
device_t dev;
uint32_t base, limit;
uint32_t basek;
uint32_t hoist;
int ii;
uint32_t carry_over;
device_t dev;
uint32_t base, limit;
uint32_t basek;
uint32_t hoist;
carry_over = (4*1024*1024) - hole_startk;
carry_over = (4*1024*1024) - hole_startk;
for(ii=7;ii>i;ii--) {
for(ii=7;ii>i;ii--) {
base = f1_read_config32(0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
base = f1_read_config32(0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
limit = f1_read_config32(0x44 + (ii << 3));
f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
}
limit = f1_read_config32(0x44 + (i << 3));
f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
dev = __f1_dev[i];
base = pci_read_config32(dev, 0x40 + (i << 3));
basek = (base & 0xffff0000) >> 2;
f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
}
limit = f1_read_config32(0x44 + (i << 3));
f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
dev = __f1_dev[i];
base = pci_read_config32(dev, 0x40 + (i << 3));
basek = (base & 0xffff0000) >> 2;
if(basek == hole_startk) {
//don't need set memhole here, because hole off set will be 0, overflow
//so need to change base reg instead, new basek will be 4*1024*1024
@ -880,19 +880,19 @@ static uint32_t hoist_memory(unsigned long hole_startk, int i)
base |= (4*1024*1024)<<2;
f1_write_config32(0x40 + (i<<3), base);
}
else
else
{
hoist = /* hole start address */
((hole_startk << 10) & 0xff000000) +
/* hole address to memory controller address */
(((basek + carry_over) >> 6) & 0x0000ff00) +
/* enable */
1;
pci_write_config32(dev, 0xf0, hoist);
hoist = /* hole start address */
((hole_startk << 10) & 0xff000000) +
/* hole address to memory controller address */
(((basek + carry_over) >> 6) & 0x0000ff00) +
/* enable */
1;
pci_write_config32(dev, 0xf0, hoist);
}
return carry_over;
return carry_over;
}
#endif
@ -911,68 +911,68 @@ static void pci_domain_set_resources(device_t dev)
#endif
#if 0
/* Place the IO devices somewhere safe */
io = find_resource(dev, 0);
io->base = DEVICE_IO_START;
/* Place the IO devices somewhere safe */
io = find_resource(dev, 0);
io->base = DEVICE_IO_START;
#endif
#if CONFIG_PCI_64BIT_PREF_MEM == 1
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
mem1 = find_resource(dev, 1);
mem2 = find_resource(dev, 2);
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
mem1 = find_resource(dev, 1);
mem2 = find_resource(dev, 2);
#if 1
printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
#endif
/* See if both resources have roughly the same limits */
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
{
/* If so place the one with the most stringent alignment first
*/
if (mem2->align > mem1->align) {
struct resource *tmp;
tmp = mem1;
mem1 = mem2;
mem2 = tmp;
}
/* Now place the memory as high up as it will go */
mem2->base = resource_max(mem2);
mem1->limit = mem2->base - 1;
mem1->base = resource_max(mem1);
}
else {
/* Place the resources as high up as they will go */
mem2->base = resource_max(mem2);
mem1->base = resource_max(mem1);
}
/* See if both resources have roughly the same limits */
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
{
/* If so place the one with the most stringent alignment first
*/
if (mem2->align > mem1->align) {
struct resource *tmp;
tmp = mem1;
mem1 = mem2;
mem2 = tmp;
}
/* Now place the memory as high up as it will go */
mem2->base = resource_max(mem2);
mem1->limit = mem2->base - 1;
mem1->base = resource_max(mem1);
}
else {
/* Place the resources as high up as they will go */
mem2->base = resource_max(mem2);
mem1->base = resource_max(mem1);
}
#if 1
printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
#endif
last = &dev->resource[dev->resources];
for(resource = &dev->resource[0]; resource < last; resource++)
{
last = &dev->resource[dev->resources];
for(resource = &dev->resource[0]; resource < last; resource++)
{
#if 1
resource->flags |= IORESOURCE_ASSIGNED;
resource->flags &= ~IORESOURCE_STORED;
resource->flags |= IORESOURCE_ASSIGNED;
resource->flags &= ~IORESOURCE_STORED;
#endif
compute_allocate_resource(&dev->link[0], resource,
BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
compute_allocate_resource(&dev->link[0], resource,
BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
resource->flags |= IORESOURCE_STORED;
report_resource_stored(dev, resource, "");
resource->flags |= IORESOURCE_STORED;
report_resource_stored(dev, resource, "");
}
}
#endif
@ -990,50 +990,50 @@ static void pci_domain_set_resources(device_t dev)
#endif
#if HW_MEM_HOLE_SIZEK != 0
/* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
* if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
* otherwise We reset the hole to the mmio_basek
*/
#if K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0()) {
#endif
/* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
* if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
* otherwise We reset the hole to the mmio_basek
*/
#if K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0()) {
#endif
mem_hole = get_hw_mem_hole_info();
if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore
mmio_basek = mem_hole.hole_startk;
if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore
mmio_basek = mem_hole.hole_startk;
reset_memhole = 0;
}
}
//mmio_basek = 3*1024*1024; // for debug to meet boundary
if(reset_memhole) {
if(mem_hole.node_id!=-1) { // We need to select HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....!
// We need to reset our Mem Hole, because We want more big HOLE than we already set
//Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead
disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
// We need to reset our Mem Hole, because We want more big HOLE than we already set
//Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead
disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
}
#if HW_MEM_HOLE_SIZE_AUTO_INC == 1
//We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
uint32_t basek_pri;
for (i = 0; i < 8; i++) {
uint32_t base;
uint32_t basek_pri;
for (i = 0; i < 8; i++) {
uint32_t base;
uint32_t basek;
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
basek = (base & 0xffff0000) >> 2;
if(mmio_basek == basek) {
mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node
break;
mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node
break;
}
basek_pri = basek;
}
#endif
}
}
#endif
}
#if K8_REV_F_SUPPORT == 0
} // is_cpu_pre_e0
@ -1060,12 +1060,12 @@ static void pci_domain_set_resources(device_t dev)
idx += 0x10;
basek = (8*64)+(16*16);
sizek = limitk - ((8*64)+(16*16));
}
// printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
// printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
/* See if I need to split the region to accomodate pci memory space */
if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
if (basek <= mmio_basek) {
@ -1077,13 +1077,13 @@ static void pci_domain_set_resources(device_t dev)
sizek -= pre_sizek;
}
#if HW_MEM_HOLE_SIZEK != 0
if(reset_memhole)
if(reset_memhole)
#if K8_REV_F_SUPPORT == 0
if(!is_cpu_pre_e0() )
if(!is_cpu_pre_e0() )
#endif
sizek += hoist_memory(mmio_basek,i);
sizek += hoist_memory(mmio_basek,i);
#endif
basek = mmio_basek;
}
if ((basek + sizek) <= 4*1024*1024) {
@ -1108,8 +1108,8 @@ static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
for(reg = 0xe0; reg <= 0xec; reg += 4) {
f1_write_config32(reg, 0);
}
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
/* Tune the hypertransport transaction for best performance.
* Including enabling relaxed ordering if it is safe.
*/
@ -1151,7 +1151,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
int i,j;
unsigned nb_cfg_54;
unsigned siblings;
int e0_later_single_core;
int e0_later_single_core;
int disable_siblings;
nb_cfg_54 = 0;
@ -1179,7 +1179,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
}
sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1;
if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
{
@ -1187,11 +1187,11 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
if(bsp_apicid == 0) {
/* bsp apic id is not changed */
sysconf.apicid_offset = APIC_ID_OFFSET;
} else
} else
{
sysconf.lift_bsp_apicid = 1;
}
}
}
/* Find which cpus are present */
@ -1233,25 +1233,25 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
printk_debug(" %s siblings=%d\n", dev_path(dev), j);
if(nb_cfg_54) {
// For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
// For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
// ----> you can mixed single core e0 and dual core e0 at any sequence
// That is the typical case
if(j == 0 ){
if(j == 0 ){
#if K8_REV_F_SUPPORT == 0
e0_later_single_core = is_e0_later_in_bsp(i); // single core
e0_later_single_core = is_e0_later_in_bsp(i); // single core
#else
e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
#endif
} else {
e0_later_single_core = 0;
}
if(e0_later_single_core) {
} else {
e0_later_single_core = 0;
}
if(e0_later_single_core) {
printk_debug("\tFound Rev E or Rev F later single core\r\n");
j=1;
j=1;
}
if(siblings > j ) {
}
else {
@ -1261,27 +1261,27 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
siblings = j;
}
}
unsigned jj;
if(e0_later_single_core || disable_siblings) {
jj = 0;
} else
} else
{
jj = siblings;
}
#if 0
#if 0
jj = 0; // if create cpu core1 path in amd_siblings by core0
#endif
for (j = 0; j <=jj; j++ ) {
for (j = 0; j <=jj; j++ ) {
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.u.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
/* See if I can find the cpu */
cpu = find_dev_path(cpu_bus, &cpu_path);
/* Enable the cpu if I have the processor */
if (dev && dev->enabled) {
if (!cpu) {
@ -1291,7 +1291,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
cpu->enabled = 1;
}
}
/* Disable the cpu if I don't have the processor */
if (cpu && (!dev || !dev->enabled)) {
cpu->enabled = 0;
@ -1301,14 +1301,14 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
if (cpu) {
cpu->path.u.apic.node_id = i;
cpu->path.u.apic.core_id = j;
if(sysconf.enabled_apic_ext_id) {
if(sysconf.lift_bsp_apicid) {
if(sysconf.enabled_apic_ext_id) {
if(sysconf.lift_bsp_apicid) {
cpu->path.u.apic.apic_id += sysconf.apicid_offset;
} else
} else
{
if (cpu->path.u.apic.apic_id != 0)
cpu->path.u.apic.apic_id += sysconf.apicid_offset;
}
if (cpu->path.u.apic.apic_id != 0)
cpu->path.u.apic.apic_id += sysconf.apicid_offset;
}
}
printk_debug("CPU: %s %s\n",
dev_path(cpu), cpu->enabled?"enabled":"disabled");
@ -1324,7 +1324,7 @@ static void cpu_bus_init(device_t dev)
initialize_cpus(&dev->link[0]);
}
static void cpu_bus_noop(device_t dev)
static void cpu_bus_noop(device_t dev)
{
}

424
src/northbridge/amd/amdk8/raminit.c
View File

@ -4,7 +4,7 @@
2005.02 yhlu add E0 memory hole support
*/
#if K8_REV_F_SUPPORT == 1
#include "raminit_f.c"
#include "raminit_f.c"
#else
#include <cpu/x86/mem.h>
@ -67,7 +67,7 @@ static void setup_resource_map(const unsigned int *register_values, int max)
static int controller_present(const struct mem_controller *ctrl)
{
return pci_read_config32(ctrl->f0, 0) == 0x11001022;
return pci_read_config32(ctrl->f0, 0) == 0x11001022;
}
#if RAMINIT_SYSINFO==1
@ -198,7 +198,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
* [29:21] Address Mask (33-25)
* The bits with an address mask of 1 are excluded from address comparison
* [31:30] Reserved
*
*
*/
PCI_ADDR(0, 0x18, 2, 0x60), 0xC01f01ff, 0x00000000,
PCI_ADDR(0, 0x18, 2, 0x64), 0xC01f01ff, 0x00000000,
@ -211,7 +211,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
/* DRAM Bank Address Mapping Register
* F2:0x80
* Specify the memory module size
* [ 2: 0] CS1/0
* [ 2: 0] CS1/0
* [ 6: 4] CS3/2
* [10: 8] CS5/4
* [14:12] CS7/6
@ -222,7 +222,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
* 100 = 512Mbyte (Rows = 13 & Col = 11)|(Rows = 14 & Col = 10)
* 101 = 1Gbyte (Rows = 14 & Col = 11)|(Rows = 13 & Col = 12)
* 110 = 2Gbyte (Rows = 14 & Col = 12)
* 111 = reserved
* 111 = reserved
* [ 3: 3] Reserved
* [ 7: 7] Reserved
* [11:11] Reserved
@ -338,8 +338,8 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
* 0 = Disabled
* 1 = Enabled
* [ 3: 3] Disable DQS Hystersis (FIXME handle this one carefully)
* 0 = Enable DQS input filter
* 1 = Disable DQS input filtering
* 0 = Enable DQS input filter
* 1 = Disable DQS input filtering
* [ 7: 4] Reserved
* [ 8: 8] DRAM_Init
* 0 = Initialization done or not yet started.
@ -396,12 +396,12 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
* 111 = Oldest entry in DCQ can be bypassed 7 times
* [31:28] Reserved
*/
PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000,
(4 << 25)|(0 << 24)|
(0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)|
(1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)|
(2 << 14)|(0 << 13)|(0 << 12)|
(0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)|
PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000,
(4 << 25)|(0 << 24)|
(0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)|
(1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)|
(2 << 14)|(0 << 13)|(0 << 12)|
(0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)|
(0 << 3) |(0 << 1) |(0 << 0),
/* DRAM Config High Register
* F2:0x94
@ -548,10 +548,10 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
int max;
#if 1
if (!controller_present(ctrl)) {
// print_debug("No memory controller present\r\n");
return;
}
if (!controller_present(ctrl)) {
// print_debug("No memory controller present\r\n");
return;
}
#endif
print_spew("setting up CPU");
print_spew_hex8(ctrl->node_id);
@ -563,8 +563,8 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
unsigned long reg;
#if 0
#if CONFIG_USE_PRINTK_IN_CAR
prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]);
#else
prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]);
#else
print_spew_hex32(register_values[i]);
print_spew(" <-");
print_spew_hex32(register_values[i+2]);
@ -602,7 +602,7 @@ static void hw_enable_ecc(const struct mem_controller *ctrl)
dcl &= ~DCL_DimmEccEn;
}
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
}
static int is_dual_channel(const struct mem_controller *ctrl)
@ -614,7 +614,7 @@ static int is_dual_channel(const struct mem_controller *ctrl)
static int is_opteron(const struct mem_controller *ctrl)
{
/* Test to see if I am an Opteron.
/* Test to see if I am an Opteron.
* FIXME Socket 939 based Athlon64 have dual channel capability,
* too, so we need a better test for Opterons
*/
@ -684,7 +684,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
if (value < 0) goto hw_err;
value &= 0xff;
value <<= 8;
low = spd_read_byte(device, 6); /* (low byte) */
if (low < 0) goto hw_err;
value = value | (low & 0xff);
@ -743,20 +743,20 @@ static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz
if (sz.side1 != sz.side2) {
sz.side2 = 0;
}
/* For each base register.
* Place the dimm size in 32 MB quantities in the bits 31 - 21.
* The initialize dimm size is in bits.
* Set the base enable bit0.
*/
base0 = base1 = 0;
/* Make certain side1 of the dimm is at least 32MB */
if (sz.side1 >= (25 +3)) {
base0 = (1 << ((sz.side1 - (25 + 3)) + 21)) | 1;
}
/* Make certain side2 of the dimm is at least 32MB */
if (sz.side2 >= (25 + 3)) {
base1 = (1 << ((sz.side2 - (25 + 3)) + 21)) | 1;
@ -810,9 +810,9 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz,
map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
map &= ~(0xf << (index * 4));
#if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) {
map &= ~(0xf << ( (index + 2) * 4));
}
if(sz.rank == 4) {
map &= ~(0xf << ( (index + 2) * 4));
}
#endif
@ -821,29 +821,29 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz,
if(is_cpu_pre_d0()) {
map |= (sz.side1 - (25 + 3)) << (index *4);
#if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) {
map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4);
}
if(sz.rank == 4) {
map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4);
}
#endif
}
else {
map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4);
#if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) {
map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4);
}
if(sz.rank == 4) {
map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4);
}
#endif
}
}
pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
}
static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
{
int i;
for(i = 0; i < DIMM_SOCKETS; i++) {
struct dimm_size sz;
if (!(dimm_mask & (1 << i))) {
@ -913,11 +913,11 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk)
*/
if (tom_k >= 0x003f0000) {
#if HW_MEM_HOLE_SIZEK != 0
if(hole_startk != 0) {
tom_k = hole_startk;
} else
if(hole_startk != 0) {
tom_k = hole_startk;
} else
#endif
tom_k = 0x3f0000;
tom_k = 0x3f0000;
}
msr.lo = (tom_k & 0x003fffff) << 10;
msr.hi = (tom_k & 0xffc00000) >> 22;
@ -927,29 +927,29 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk)
static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
{
/* 35 - 25 */
static const uint8_t csbase_low_shift[] = {
static const uint8_t csbase_low_shift[] = {
/* 32MB */ (13 - 4),
/* 64MB */ (14 - 4),
/* 128MB */ (14 - 4),
/* 128MB */ (14 - 4),
/* 256MB */ (15 - 4),
/* 512MB */ (15 - 4),
/* 1GB */ (16 - 4),
/* 2GB */ (16 - 4),
/* 2GB */ (16 - 4),
};
static const uint8_t csbase_low_d0_shift[] = {
/* 32MB */ (13 - 4),
/* 64MB */ (14 - 4),
/* 128MB */ (14 - 4),
static const uint8_t csbase_low_d0_shift[] = {
/* 32MB */ (13 - 4),
/* 64MB */ (14 - 4),
/* 128MB */ (14 - 4),
/* 128MB */ (15 - 4),
/* 256MB */ (15 - 4),
/* 512MB */ (15 - 4),
/* 256MB */ (16 - 4),
/* 512MB */ (16 - 4),
/* 1GB */ (16 - 4),
/* 256MB */ (15 - 4),
/* 512MB */ (15 - 4),
/* 256MB */ (16 - 4),
/* 512MB */ (16 - 4),
/* 1GB */ (16 - 4),
/* 1GB */ (17 - 4),
/* 2GB */ (17 - 4),
};
/* 2GB */ (17 - 4),
};
/* cs_base_high is not changed */
@ -970,9 +970,9 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
unsigned size;
unsigned cs_mode;
uint32_t value;
value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
/* Is it enabled? */
if (!(value & 1)) {
continue;
@ -988,15 +988,15 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
}
value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
cs_mode =( value >> ((index>>1)*4)) & 0xf;
if(cs_mode == 0 ) continue;
if(common_cs_mode == 0) {
common_cs_mode = cs_mode;
}
/* The size differed fail */
if(common_cs_mode != cs_mode) {
return 0;
}
cs_mode =( value >> ((index>>1)*4)) & 0xf;
if(cs_mode == 0 ) continue;
if(common_cs_mode == 0) {
common_cs_mode = cs_mode;
}
/* The size differed fail */
if(common_cs_mode != cs_mode) {
return 0;
}
}
/* Chip selects can only be interleaved when there is
@ -1011,26 +1011,26 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
if(is_cpu_pre_d0()){
csbase_inc = 1 << csbase_low_shift[common_cs_mode];
if(is_dual_channel(ctrl)) {
/* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
// print_debug("8 4GB chip selects cannot be interleaved\r\n");
return 0;
}
/* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
// print_debug("8 4GB chip selects cannot be interleaved\r\n");
return 0;
}
csbase_inc <<=1;
}
}
else {
csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode];
if(is_dual_channel(ctrl)) {
if( (bits==3) && (common_cs_mode > 8)) {
// print_debug("8 cs_mode>8 chip selects cannot be interleaved\r\n");
return 0;
if( (bits==3) && (common_cs_mode > 8)) {
// print_debug("8 cs_mode>8 chip selects cannot be interleaved\r\n");
return 0;
}
csbase_inc <<=1;
}
}
}
/* Compute the initial values for csbase and csbask.
/* Compute the initial values for csbase and csbask.
* In csbase just set the enable bit and the base to zero.
* In csmask set the mask bits for the size and page level interleave.
*/
@ -1049,7 +1049,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
pci_write_config32(ctrl->f2, DRAM_CSMASK + (index << 2), csmask);
csbase += csbase_inc;
}
print_spew("Interleaved\r\n");
/* Return the memory size in K */
@ -1077,12 +1077,12 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl)
if (!(value & 1)) {
continue;
}
/* Is it greater? */
if (value <= csbase) {
continue;
}
/* Has it already been selected */
if (tom & (1 << (index + 24))) {
continue;
@ -1116,7 +1116,7 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl)
pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
/* Write the new mask register */
pci_write_config32(ctrl->f2, DRAM_CSMASK + (canidate << 2), csmask);
}
/* Return the memory size in K */
return (tom & ~0xff000000) << 15;
@ -1164,8 +1164,8 @@ static void order_dimms(const struct mem_controller *ctrl)
static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask)
{
print_debug("disabling dimm");
print_debug_hex8(index);
print_debug("disabling dimm");
print_debug_hex8(index);
print_debug("\r\n");
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
@ -1194,7 +1194,7 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, long
/* Registered dimm ? */
if (value & (1 << 1)) {
registered = 1;
}
}
/* Otherwise it must be an unbuffered dimm */
else {
unbuffered = 1;
@ -1209,9 +1209,9 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, long
if (unbuffered) {
if ((has_dualch) && (!is_cpu_pre_d0())) {
dcl |= DCL_UnBufDimm; /* set DCL_DualDIMMen too? */
/* set DCL_En2T if you have non-equal DDR mem types! */
if ((cpuid_eax(1) & 0x30) == 0x30) {
/* CS[7:4] is copy of CS[3:0], should be set for 939 socket */
dcl |= DCL_UpperCSMap;
@ -1286,7 +1286,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma
};
/* If the dimms are not in pairs do not do dual channels */
if ((dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
goto single_channel;
}
/* If the cpu is not capable of doing dual channels don't do dual channels */
@ -1521,7 +1521,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
/* Make a second pass through the dimms and disable
* any that cannot support the selected memclk and cas latency.
*/
for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
int latencies;
int latency;
@ -1551,12 +1551,12 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
if ((latency != min_latency) || (index >= 3)) {
goto dimm_err;
}
/* Read the min_cycle_time for this latency */
value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
if (value < 0) goto hw_error;
/* All is good if the selected clock speed
/* All is good if the selected clock speed
* is what I need or slower.
*/
if (value <= min_cycle_time) {
@ -1571,12 +1571,12 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
#if QRANK_DIMM_SUPPORT
if(dimm_mask == (3|(3<<DIMM_SOCKETS)) ) {
int ranks = 4;
for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
int val;
if (!(dimm_mask & (1 << i))) {
continue;
}
val = spd_read_byte(ctrl->channel0[i], 5);
if (!(dimm_mask & (1 << i))) {
continue;
}
val = spd_read_byte(ctrl->channel0[i], 5);
if(val!=ranks) {
ranks = val;
break;
@ -1587,7 +1587,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
min_cycle_time = 0x60;
}
}
}
#endif
#endif
@ -1615,7 +1615,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
value |= latencies[min_latency - 2] << DTL_TCL_SHIFT;
pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
result.dimm_mask = dimm_mask;
return result;
hw_error:
@ -1844,9 +1844,9 @@ static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_pa
}
#if QRANK_DIMM_SUPPORT == 1
rank = spd_read_byte(ctrl->channel0[i], 5); /* number of physical banks */
rank = spd_read_byte(ctrl->channel0[i], 5); /* number of physical banks */
if (rank < 0) {
return -1;
return -1;
}
#endif
@ -1943,7 +1943,7 @@ static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *
if ((clocks < DTH_TRWT_MIN) || (clocks > DTH_TRWT_MAX)) {
die("Unknown Trwt\r\n");
}
dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
dth &= ~(DTH_TRWT_MASK << DTH_TRWT_SHIFT);
dth |= ((clocks - DTH_TRWT_BASE) << DTH_TRWT_SHIFT);
@ -2022,7 +2022,7 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc
if (dimms == 4) {
/* 9ns */
async_lat = 9;
}
}
else {
/* 8ns */
async_lat = 8;
@ -2059,7 +2059,7 @@ static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct
static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, long dimm_mask)
{
int i;
init_Tref(ctrl, param);
for(i = 0; i < DIMM_SOCKETS; i++) {
int rc;
@ -2076,7 +2076,7 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct
/* DRAM Timing High Register */
if ((rc = update_dimm_Tref(ctrl, param, i)) <= 0) goto dimm_err;
/* DRAM Config Low */
if ((rc = update_dimm_x4 (ctrl, param, i)) <= 0) goto dimm_err;
@ -2104,9 +2104,9 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct
}
#if RAMINIT_SYSINFO==1
static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
#else
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
#endif
{
struct spd_set_memclk_result result;
@ -2125,19 +2125,19 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
print_debug("No memory for this cpu\r\n");
return;
}
dimm_mask = spd_enable_2channels(ctrl, dimm_mask);
if (dimm_mask < 0)
dimm_mask = spd_enable_2channels(ctrl, dimm_mask);
if (dimm_mask < 0)
goto hw_spd_err;
dimm_mask = spd_set_ram_size(ctrl , dimm_mask);
if (dimm_mask < 0)
dimm_mask = spd_set_ram_size(ctrl , dimm_mask);
if (dimm_mask < 0)
goto hw_spd_err;
dimm_mask = spd_handle_unbuffered_dimms(ctrl, dimm_mask);
if (dimm_mask < 0)
dimm_mask = spd_handle_unbuffered_dimms(ctrl, dimm_mask);
if (dimm_mask < 0)
goto hw_spd_err;
result = spd_set_memclk(ctrl, dimm_mask);
param = result.param;
dimm_mask = result.dimm_mask;
if (dimm_mask < 0)
if (dimm_mask < 0)
goto hw_spd_err;
dimm_mask = spd_set_dram_timing(ctrl, param , dimm_mask);
if (dimm_mask < 0)
@ -2154,108 +2154,108 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
#if HW_MEM_HOLE_SIZEK != 0
static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i)
{
int ii;
uint32_t carry_over;
device_t dev;
uint32_t base, limit;
uint32_t basek;
uint32_t hoist;
int j;
int ii;
uint32_t carry_over;
device_t dev;
uint32_t base, limit;
uint32_t basek;
uint32_t hoist;
int j;
carry_over = (4*1024*1024) - hole_startk;
carry_over = (4*1024*1024) - hole_startk;
for(ii=controllers - 1;ii>i;ii--) {
base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
for(ii=controllers - 1;ii>i;ii--) {
base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
for(j = 0; j < controllers; j++) {
pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
}
}
limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
for(j = 0; j < controllers; j++) {
pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
}
dev = ctrl[i].f1;
base = pci_read_config32(dev, 0x40 + (i << 3));
basek = (base & 0xffff0000) >> 2;
if(basek == hole_startk) {
//don't need set memhole here, because hole off set will be 0, overflow
//so need to change base reg instead, new basek will be 4*1024*1024
base &= 0x0000ffff;
base |= (4*1024*1024)<<2;
for(j = 0; j < controllers; j++) {
pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
}
}
for(j = 0; j < controllers; j++) {
pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
}
}
limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
for(j = 0; j < controllers; j++) {
pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
}
dev = ctrl[i].f1;
base = pci_read_config32(dev, 0x40 + (i << 3));
basek = (base & 0xffff0000) >> 2;
if(basek == hole_startk) {
//don't need set memhole here, because hole off set will be 0, overflow
//so need to change base reg instead, new basek will be 4*1024*1024
base &= 0x0000ffff;
base |= (4*1024*1024)<<2;
for(j = 0; j < controllers; j++) {
pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
}
}
else {
hoist = /* hole start address */
((hole_startk << 10) & 0xff000000) +
/* hole address to memory controller address */
(((basek + carry_over) >> 6) & 0x0000ff00) +
/* enable */
1;
pci_write_config32(dev, 0xf0, hoist);
hoist = /* hole start address */
((hole_startk << 10) & 0xff000000) +
/* hole address to memory controller address */
(((basek + carry_over) >> 6) & 0x0000ff00) +
/* enable */
1;
pci_write_config32(dev, 0xf0, hoist);
}
return carry_over;
return carry_over;
}
static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
{
uint32_t hole_startk;
int i;
uint32_t hole_startk;
int i;
hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK;
hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK;
#if HW_MEM_HOLE_SIZE_AUTO_INC == 1
#if HW_MEM_HOLE_SIZE_AUTO_INC == 1
/* We need to double check if hole_startk is valid.
* If it is equal to the dram base address in K (base_k),
* If it is equal to the dram base address in K (base_k),
* we need to decrease it.
*/
uint32_t basek_pri;
for(i=0; i<controllers; i++) {
uint32_t base;
unsigned base_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
base_k = (base & 0xffff0000) >> 2;
if(base_k == hole_startk) {
uint32_t basek_pri;
for(i=0; i<controllers; i++) {
uint32_t base;
unsigned base_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
base_k = (base & 0xffff0000) >> 2;
if(base_k == hole_startk) {
/* decrease memory hole startk to make sure it is
* in the middle of the previous node
* in the middle of the previous node
*/
hole_startk -= (base_k - basek_pri)>>1;
break; /* only one hole */
}
basek_pri = base_k;
}
hole_startk -= (base_k - basek_pri)>>1;
break; /* only one hole */
}
basek_pri = base_k;
}
#endif
/* Find node number that needs the memory hole configured */
for(i=0; i<controllers; i++) {
uint32_t base, limit;
unsigned base_k, limit_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
base_k = (base & 0xffff0000) >> 2;
limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
/* Find node number that needs the memory hole configured */
for(i=0; i<controllers; i++) {
uint32_t base, limit;
unsigned base_k, limit_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
base_k = (base & 0xffff0000) >> 2;
limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
if ((base_k <= hole_startk) && (limit_k > hole_startk)) {
unsigned end_k;
hoist_memory(controllers, ctrl, hole_startk, i);
end_k = memory_end_k(ctrl, controllers);
set_top_mem(end_k, hole_startk);
break; /* only one hole */
}
}
unsigned end_k;
hoist_memory(controllers, ctrl, hole_startk, i);
end_k = memory_end_k(ctrl, controllers);
set_top_mem(end_k, hole_startk);
break; /* only one hole */
}
}
}
@ -2369,10 +2369,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
}
#if HW_MEM_HOLE_SIZEK != 0
// init hw mem hole here
/* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
// init hw mem hole here
/* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
if(!is_cpu_pre_e0())
set_hw_mem_hole(controllers, ctrl);
set_hw_mem_hole(controllers, ctrl);
#endif
//FIXME add enable node interleaving here -- yhlu
@ -2396,7 +2396,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* The first 1M is now setup, use it */
cache_lbmem(MTRR_TYPE_WRBACK);
print_debug(" done\r\n");
#endif
}
@ -2408,24 +2408,24 @@ static void set_sysinfo_in_ram(unsigned val)
static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr)
{
int i;
int j;
struct mem_controller *ctrl;
for(i=0;i<controllers; i++) {
ctrl = &ctrl_a[i];
ctrl->node_id = i;
ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
ctrl->f1 = PCI_DEV(0, 0x18+i, 1);
ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
int i;
int j;
struct mem_controller *ctrl;
for(i=0;i<controllers; i++) {
ctrl = &ctrl_a[i];
ctrl->node_id = i;
ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
ctrl->f1 = PCI_DEV(0, 0x18+i, 1);
ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
if(spd_addr == (void *)0) continue;
if(spd_addr == (void *)0) continue;
for(j=0;j<DIMM_SOCKETS;j++) {
ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];
}
}
for(j=0;j<DIMM_SOCKETS;j++) {
ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];
}
}
}
#endif

1504
src/northbridge/amd/amdk8/raminit_f_dqs.c
View File

File diff suppressed because it is too large Load Diff

104
src/northbridge/amd/amdk8/raminit_test.c
View File

@ -51,7 +51,7 @@ static uint32_t pci_read_config32(device_t dev, unsigned where)
unsigned addr;
uint32_t value;
addr = dev | where;
value = pci_register[addr] |
value = pci_register[addr] |
(pci_register[addr + 1] << 8) |
(pci_register[addr + 2] << 16) |
(pci_register[addr + 3] << 24);
@ -128,23 +128,23 @@ static void hlt(void)
unsigned long log2(unsigned long x)
{
// assume 8 bits per byte.
unsigned long i = 1 << (sizeof(x)*8 - 1);
unsigned long pow = sizeof(x) * 8 - 1;
// assume 8 bits per byte.
unsigned long i = 1 << (sizeof(x)*8 - 1);
unsigned long pow = sizeof(x) * 8 - 1;
if (! x) {
if (! x) {
static const char errmsg[] = " called with invalid parameter of 0\n";
write(STDERR_FILENO, __func__, sizeof(__func__) - 1);
write(STDERR_FILENO, errmsg, sizeof(errmsg) - 1);
hlt();
}
for(; i > x; i >>= 1, pow--)
;
hlt();
}
for(; i > x; i >>= 1, pow--)
;
return pow;
return pow;
}
typedef struct msr_struct
typedef struct msr_struct
{
unsigned lo;
unsigned hi;
@ -188,10 +188,10 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
}
static uint8_t spd_mt4lsdt464a[256] =
static uint8_t spd_mt4lsdt464a[256] =
{
0x80, 0x08, 0x04, 0x0C, 0x08, 0x01, 0x40, 0x00, 0x01, 0x70,
0x54, 0x00, 0x80, 0x10, 0x00, 0x01, 0x8F, 0x04, 0x06, 0x01,
0x80, 0x08, 0x04, 0x0C, 0x08, 0x01, 0x40, 0x00, 0x01, 0x70,
0x54, 0x00, 0x80, 0x10, 0x00, 0x01, 0x8F, 0x04, 0x06, 0x01,
0x01, 0x00, 0x0E, 0x75, 0x54, 0x00, 0x00, 0x0F, 0x0E, 0x0F,
0x25, 0x08, 0x15, 0x08, 0x15, 0x08, 0x00, 0x12, 0x01, 0x4E,
@ -200,46 +200,46 @@ static uint8_t spd_mt4lsdt464a[256] =
0x06, 0x07, 0x08, 0x09, 0x00,
};
static uint8_t spd_micron_512MB_DDR333[256] =
static uint8_t spd_micron_512MB_DDR333[256] =
{
0x80, 0x08, 0x07, 0x0d, 0x0b, 0x02, 0x48, 0x00, 0x04, 0x60,
0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x01, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x10, 0x6f, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0x01, 0x33, 0x36, 0x56, 0x44, 0x44, 0x46, 0x31,
0x32, 0x38, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43,
0x33, 0x03, 0x00, 0x03, 0x23, 0x17, 0x07, 0x5a, 0xb2, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0x80, 0x08, 0x07, 0x0d, 0x0b, 0x02, 0x48, 0x00, 0x04, 0x60,
0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x01, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x10, 0x6f, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0x01, 0x33, 0x36, 0x56, 0x44, 0x44, 0x46, 0x31,
0x32, 0x38, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43,
0x33, 0x03, 0x00, 0x03, 0x23, 0x17, 0x07, 0x5a, 0xb2, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff
};
static uint8_t spd_micron_256MB_DDR333[256] =
static uint8_t spd_micron_256MB_DDR333[256] =
{
0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00, 0x04, 0x60,
0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00, 0x04, 0x60,
0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
0x00, 0x3c, 0x48, 0x30, 0x23, 0x50, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x58, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0x01, 0x31, 0x38, 0x56, 0x44, 0x44, 0x46, 0x36,
0xff, 0xff, 0x01, 0x31, 0x38, 0x56, 0x44, 0x44, 0x46, 0x36,
0x34, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, 0x31,
0x20, 0x01, 0x00, 0x03, 0x19, 0x17, 0x05, 0xb2, 0xf4, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@ -247,17 +247,17 @@ static uint8_t spd_micron_256MB_DDR333[256] =
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
};
#define MAX_DIMMS 16
@ -273,7 +273,7 @@ static int spd_read_byte(unsigned device, unsigned address)
}
else {
device -= 0x50;
if (address > 256) {
result = -1;
}
@ -390,13 +390,13 @@ static void test1(void)
#endif
raminit_main();
#if 0
print_debug("spd_count: ");
print_debug_hex32(spd_count);
print_debug("\r\n");
#endif
}
@ -413,10 +413,10 @@ static void do_test2(int i)
print_debug("\r\nSPD will fail after: ");
print_debug_hex32(spd_fail_count);
print_debug(" accesses.\r\n");
memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
raminit_main();
done:
@ -429,7 +429,7 @@ static void test2(void)
for(i = 0; i < 0x48; i++) {
do_test2(i);
}
}
int main(int argc, char **argv)

36
src/northbridge/amd/amdk8/reset_test.c
View File

@ -54,29 +54,29 @@ static void set_bios_reset(void)
static unsigned node_link_to_bus(unsigned node, unsigned link)
{
unsigned reg;
unsigned reg;
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
unsigned config_map;
config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
if ((config_map & 3) != 3) {
continue;
}
if ((((config_map >> 4) & 7) == node) &&
(((config_map >> 8) & 3) == link))
{
return (config_map >> 16) & 0xff;
}
}
return 0;
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
unsigned config_map;
config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
if ((config_map & 3) != 3) {
continue;
}
if ((((config_map >> 4) & 7) == node) &&
(((config_map >> 8) & 3) == link))
{
return (config_map >> 16) & 0xff;
}
}
return 0;
}
static unsigned get_sblk(void)
{
uint32_t reg;
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
return ((reg>>8) & 3) ;
uint32_t reg;
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
return ((reg>>8) & 3) ;
}
static unsigned get_sbbusn(unsigned sblk)

6
src/northbridge/amd/amdk8/resourcemap.c
View File

@ -139,7 +139,7 @@ static void setup_default_resource_map(void)
* 1 = base/limit registers i are read-only
* [ 7: 4] Reserved
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
* This field defines the upper address bits of a 40bit address
* This field defines the upper address bits of a 40bit address
* that defines the start of memory-mapped I/O region i
*/
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
@ -195,7 +195,7 @@ static void setup_default_resource_map(void)
* [ 3: 2] Reserved
* [ 4: 4] VGA Enable
* 0 = VGA matches Disabled
* 1 = matches all address < 64K and where A[9:0] is in the
* 1 = matches all address < 64K and where A[9:0] is in the
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
* [ 5: 5] ISA Enable
* 0 = ISA matches Disabled
@ -203,7 +203,7 @@ static void setup_default_resource_map(void)
* from matching agains this base/limit pair
* [11: 6] Reserved
* [24:12] PCI I/O Base i
* This field defines the start of PCI I/O region n
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,

346
src/northbridge/amd/amdk8/setup_resource_map.c
View File

@ -1,44 +1,44 @@
#define RES_DEBUG 0
static void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base)
{
int i;
{
int i;
// print_debug("setting up resource map offset....");
#if 0
print_debug("\r\n");
print_debug("\r\n");
#endif
for(i = 0; i < max; i += 3) {
device_t dev;
unsigned where;
unsigned long reg;
for(i = 0; i < max; i += 3) {
device_t dev;
unsigned where;
unsigned long reg;
#if 0
#if CONFIG_USE_PRINTK_IN_CAR
prink_debug("%08x <- %08x\r\n", register_values[i] + offset_pci_dev, register_values[i+2]);
#else
print_debug_hex32(register_values[i] + offset_pci_dev);
print_debug(" <-");
print_debug_hex32(register_values[i+2]);
print_debug("\r\n");
#endif
prink_debug("%08x <- %08x\r\n", register_values[i] + offset_pci_dev, register_values[i+2]);
#else
print_debug_hex32(register_values[i] + offset_pci_dev);
print_debug(" <-");
print_debug_hex32(register_values[i+2]);
print_debug("\r\n");
#endif
#endif
dev = (register_values[i] & ~0xfff) + offset_pci_dev;
where = register_values[i] & 0xfff;
reg = pci_read_config32(dev, where);
reg &= register_values[i+1];
reg |= register_values[i+2] + offset_io_base;
pci_write_config32(dev, where, reg);
dev = (register_values[i] & ~0xfff) + offset_pci_dev;
where = register_values[i] & 0xfff;
reg = pci_read_config32(dev, where);
reg &= register_values[i+1];
reg |= register_values[i+2] + offset_io_base;
pci_write_config32(dev, where, reg);
#if 0
reg = pci_read_config32(register_values[i]);
reg &= register_values[i+1];
reg |= register_values[i+2] & ~register_values[i+1];
pci_write_config32(register_values[i], reg);
reg = pci_read_config32(register_values[i]);
reg &= register_values[i+1];
reg |= register_values[i+2] & ~register_values[i+1];
pci_write_config32(register_values[i], reg);
#endif
}
}
// print_debug("done.\r\n");
}
#define RES_PCI_IO 0x10
#define RES_PORT_IO_8 0x22
#define RES_PORT_IO_8 0x22
#define RES_PORT_IO_32 0x20
#define RES_MEM_IO 0x40
@ -57,29 +57,29 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int
for(i = 0; i < max; i += 4) {
#if RES_DEBUG
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
i>>2, register_values[i],
register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
register_values[i+2],
printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
i>>2, register_values[i],
register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
register_values[i+2],
register_values[i+3] + ( ( (register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0)
);
#else
print_debug_hex16(i>>2);
print_debug(": ");
print_debug_hex8(register_values[i]);
print_debug(" ");
print_debug_hex32(register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0) );
print_debug(" <- & ");
print_debug_hex32(register_values[i+2]);
print_debug(" | ");
print_debug_hex32(register_values[i+3] +
#else
print_debug_hex16(i>>2);
print_debug(": ");
print_debug_hex8(register_values[i]);
print_debug(" ");
print_debug_hex32(register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0) );
print_debug(" <- & ");
print_debug_hex32(register_values[i+2]);
print_debug(" | ");
print_debug_hex32(register_values[i+3] +
(((register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0)
);
print_debug("\r\n");
print_debug("\r\n");
#endif
#endif
switch (register_values[i]) {
case RES_PCI_IO: //PCI
case RES_PCI_IO: //PCI
{
device_t dev;
unsigned where;
@ -115,7 +115,7 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int
}
break;
#if 0
case RES_MEM_IO: //mem
case RES_MEM_IO: //mem
{
unsigned where;
unsigned long reg;
@ -127,10 +127,10 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int
}
break;
#endif
} // switch
}
#if RES_DEBUG
@ -138,195 +138,195 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int
#endif
}
static void setup_resource_map_x(const unsigned int *register_values, int max)
{
int i;
{
int i;
#if RES_DEBUG
print_debug("setting up resource map ex offset....");
print_debug("setting up resource map ex offset....");
#endif
#if RES_DEBUG
print_debug("\r\n");
print_debug("\r\n");
#endif
for(i = 0; i < max; i += 4) {
for(i = 0; i < max; i += 4) {
#if RES_DEBUG
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
#else
print_debug_hex16(i/4);
print_debug(": ");
print_debug_hex8(register_values[i]);
print_debug(" ");
print_debug_hex32(register_values[i+1]);
print_debug(" <- & ");
print_debug_hex32(register_values[i+2]);
print_debug(" | ");
print_debug_hex32(register_values[i+3]);
print_debug("\r\n");
#endif
printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
#else
print_debug_hex16(i/4);
print_debug(": ");
print_debug_hex8(register_values[i]);
print_debug(" ");
print_debug_hex32(register_values[i+1]);
print_debug(" <- & ");
print_debug_hex32(register_values[i+2]);
print_debug(" | ");
print_debug_hex32(register_values[i+3]);
print_debug("\r\n");
#endif
#endif
switch (register_values[i]) {
case RES_PCI_IO: //PCI
{
device_t dev;
unsigned where;
unsigned long reg;
dev = register_values[i+1] & ~0xfff;
where = register_values[i+1] & 0xfff;
reg = pci_read_config32(dev, where);
reg &= register_values[i+2];
reg |= register_values[i+3];
pci_write_config32(dev, where, reg);
}
break;
case RES_PORT_IO_8: // io 8
{
unsigned where;
unsigned reg;
where = register_values[i+1];
reg = inb(where);
reg &= register_values[i+2];
reg |= register_values[i+3];
outb(reg, where);
}
break;
case RES_PORT_IO_32: //io32
{
unsigned where;
unsigned long reg;
where = register_values[i+1];
reg = inl(where);
reg &= register_values[i+2];
reg |= register_values[i+3];
outl(reg, where);
}
break;
switch (register_values[i]) {
case RES_PCI_IO: //PCI
{
device_t dev;
unsigned where;
unsigned long reg;
dev = register_values[i+1] & ~0xfff;
where = register_values[i+1] & 0xfff;
reg = pci_read_config32(dev, where);
reg &= register_values[i+2];
reg |= register_values[i+3];
pci_write_config32(dev, where, reg);
}
break;
case RES_PORT_IO_8: // io 8
{
unsigned where;
unsigned reg;
where = register_values[i+1];
reg = inb(where);
reg &= register_values[i+2];
reg |= register_values[i+3];
outb(reg, where);
}
break;
case RES_PORT_IO_32: //io32
{
unsigned where;
unsigned long reg;
where = register_values[i+1];
reg = inl(where);
reg &= register_values[i+2];
reg |= register_values[i+3];
outl(reg, where);
}
break;
#if 0
case RES_MEM_IO: //mem
{
unsigned where;
unsigned long reg;
where = register_values[i+1];
reg = read32(where);
reg &= register_values[i+2];
reg |= register_values[i+3];
write32( where, reg);
}
break;
case RES_MEM_IO: //mem
{
unsigned where;
unsigned long reg;
where = register_values[i+1];
reg = read32(where);
reg &= register_values[i+2];
reg |= register_values[i+3];
write32( where, reg);
}
break;
#endif
} // switch
} // switch
}
}
#if RES_DEBUG
print_debug("done.\r\n");
print_debug("done.\r\n");
#endif
}
static void setup_iob_resource_map(const unsigned int *register_values, int max)
{
int i;
int i;
for(i = 0; i < max; i += 3) {
unsigned where;
unsigned where;
unsigned reg;
where = register_values[i];
#if 0
udelay(2000);
print_debug_hex16(where);
udelay(2000);
print_debug_hex16(where);
#endif
reg = inb(where);
#if 0
print_debug("=");
print_debug_hex8(reg);
#endif
reg &= register_values[i+1];
reg |= register_values[i+2];
#if 0
print_debug(" <- ");
print_debug_hex8(reg);
#endif
outb(reg, where);
#if 0
print_debug(" -> ");
reg = inb(where);
print_debug_hex8(reg);
#if 0
print_debug("=");
print_debug_hex8(reg);
#endif
reg &= register_values[i+1];
reg |= register_values[i+2];
#if 0
print_debug(" <- ");
print_debug_hex8(reg);
#endif
outb(reg, where);
#if 0
print_debug(" -> ");
reg = inb(where);
print_debug_hex8(reg);
print_debug("\r\n");
#endif
}
}
}
static void setup_io_resource_map(const unsigned int *register_values, int max)
{
int i;
int i;
for(i = 0; i < max; i += 3) {
unsigned where;
unsigned where;
unsigned long reg;
where = register_values[i];
#if 0
udelay(2000);
print_debug_hex16(where);
udelay(2000);
print_debug_hex16(where);
#endif
reg = inl(where);
reg = inl(where);
#if 0
udelay(2000);
print_debug("=");
print_debug_hex32(reg);
print_debug("=");
print_debug_hex32(reg);
#endif
reg &= register_values[i+1];
reg |= register_values[i+2];
reg &= register_values[i+1];
reg |= register_values[i+2];
#if 0
udelay(2000);
print_debug(" <- ");
print_debug_hex32(reg);
print_debug(" <- ");
print_debug_hex32(reg);
#endif
outl(reg, where);
outl(reg, where);
#if 0
udelay(2000);
print_debug(" -> ");
reg = inl(where);
print_debug_hex32(reg);
print_debug(" -> ");
reg = inl(where);
print_debug_hex32(reg);
print_debug("\r\n");
#endif
}
}
}
#if 0
static void setup_mem_resource_map(const unsigned int *register_values, int max)
{
int i;
int i;
for(i = 0; i < max; i += 3) {
unsigned where;
unsigned where;
unsigned long reg;
#if 0
print_debug_hex32(register_values[i]);
print_debug(" <-");
print_debug_hex32(register_values[i+2]);
print_debug_hex32(register_values[i]);
print_debug(" <-");
print_debug_hex32(register_values[i+2]);
#endif
where = register_values[i];
reg = read32(where);
reg &= register_values[i+1];
reg |= register_values[i+2];
write32( where, reg);
where = register_values[i];
reg = read32(where);
reg &= register_values[i+1];
reg |= register_values[i+2];
write32( where, reg);
#if 0
print_debug(" RB ");
reg = read32(where);
print_debug_hex32(reg);
print_debug("\r\n");
print_debug(" RB ");
reg = read32(where);
print_debug_hex32(reg);
print_debug("\r\n");
#endif
}
}
}
#endif

24
src/northbridge/amd/amdk8/spd_ddr2.h
View File

@ -1,7 +1,7 @@
/* SPDs for DDR2 SDRAM */
#define SPD_MEM_TYPE 2
#define SPD_MEM_TYPE_SDRAM_DDR 0x07
#define SPD_MEM_TYPE_SDRAM_DDR2 0x08
#define SPD_MEM_TYPE 2
#define SPD_MEM_TYPE_SDRAM_DDR 0x07
#define SPD_MEM_TYPE_SDRAM_DDR2 0x08
#define SPD_DIMM_TYPE 20 /* x bit0 or bit4 =1 mean registered*/
#define SPD_DIMM_TYPE_RDIMM (1<<0)
@ -11,9 +11,9 @@
#define SPD_DIMM_TYPE_mRDIMM (1<<4)
#define SPD_DIMM_TYPE_mUDIMM (1<<5)
#define SPD_MOD_ATTRIB 21
#define SPD_MOD_ATTRIB_DIFCK 0x20
#define SPD_MOD_ATTRIB_REGADC 0x11 /* x */
#define SPD_MOD_ATTRIB_PROBE 0x40
#define SPD_MOD_ATTRIB_DIFCK 0x20
#define SPD_MOD_ATTRIB_REGADC 0x11 /* x */
#define SPD_MOD_ATTRIB_PROBE 0x40
#define SPD_DEV_ATTRIB 22 /* Device attributes --- general */
#define SPD_DIMM_CONF_TYPE 11
@ -22,16 +22,16 @@
#define SPD_ROW_NUM 3 /* Number of Row addresses */
#define SPD_COL_NUM 4 /* Number of Column addresses */
#define SPD_BANK_NUM 17 /* SDRAM Device attributes - Number of Banks on SDRAM device, it could be 0x4, 0x8, so address lines for that would be 2, and 3 */
#define SPD_MOD_ATTRIB_RANK 5 /* include Number of Ranks bit [2:0], Package (bit4, 1=stack, 0=planr), Height bit[7:5] */
#define SPD_BANK_NUM 17 /* SDRAM Device attributes - Number of Banks on SDRAM device, it could be 0x4, 0x8, so address lines for that would be 2, and 3 */
#define SPD_MOD_ATTRIB_RANK 5 /* include Number of Ranks bit [2:0], Package (bit4, 1=stack, 0=planr), Height bit[7:5] */
#define SPD_MOD_ATTRIB_RANK_NUM_SHIFT 0
#define SPD_MOD_ATTRIB_RANK_NUM_MASK 0x07
#define SPD_MOD_ATTRIB_RANK_NUM_MASK 0x07
#define SPD_MOD_ATTRIB_RANK_NUM_BASE 1
#define SPD_MOD_ATTRIB_RANK_NUM_MIN 1
#define SPD_MOD_ATTRIB_RANK_NUM_MAX 8
#define SPD_RANK_SIZE 31 /* Only one bit is set */
#define SPD_RANK_SIZE 31 /* Only one bit is set */
#define SPD_RANK_SIZE_1GB (1<<0)
#define SPD_RANK_SIZE_2GB (1<<1)
#define SPD_RANK_SIZE_4GB (1<<2)
@ -58,7 +58,7 @@
#define SPD_TRAS 30
#define SPD_TWR 36 /* x */
#define SPD_TWTR 37 /* x */
#define SPD_TRTP 38 /* x */
#define SPD_TRTP 38 /* x */
#define SPD_TRC 41 /* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)] ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0}*/
#define SPD_TRFC 42 /* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)] + (val40 & 1)*256*/

108
src/northbridge/amd/amdk8/ssdt.dsl
View File

@ -10,45 +10,45 @@ DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-K8", "AMD-ACPI", 100925440)
Scope (\_SB.PCI0)
{
Name (BUSN, Package (0x04)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444
})
Name (MMIO, Package (0x10)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888,
0x99999999,
0xaaaaaaaa,
0xbbbbbbbb,
0xcccccccc,
0xdddddddd,
0xeeeeeeee,
0x11111111,
0x22222222
})
Name (PCIO, Package (0x08)
{
0x77777777,
0x88888888,
0x99999999,
0xaaaaaaaa,
0xbbbbbbbb,
0xcccccccc,
0xdddddddd,
0xeeeeeeee
})
Name (SBLK, 0x11)
Name (TOM1, 0xaaaaaaaa)
Name (BUSN, Package (0x04)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444
})
Name (MMIO, Package (0x10)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888,
0x99999999,
0xaaaaaaaa,
0xbbbbbbbb,
0xcccccccc,
0xdddddddd,
0xeeeeeeee,
0x11111111,
0x22222222
})
Name (PCIO, Package (0x08)
{
0x77777777,
0x88888888,
0x99999999,
0xaaaaaaaa,
0xbbbbbbbb,
0xcccccccc,
0xdddddddd,
0xeeeeeeee
})
Name (SBLK, 0x11)
Name (TOM1, 0xaaaaaaaa)
Name (SBDN, 0xbbbbbbbb)
Name (HCLK, Package (0x08)
{
@ -56,22 +56,22 @@ DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-K8", "AMD-ACPI", 100925440)
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888
0x55555555,
0x66666666,
0x77777777,
0x88888888
})
Name (HCDN, Package (0x08)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888
})
Name (HCDN, Package (0x08)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888
})
Name (CBST, 0x88)
}
}