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Whitespace cleanup (trivial). 

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson 2008-10-02 19:20:22 +00:00
parent 7f3d48c9af
commit d61ada6555
18 changed files with 2656 additions and 2655 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/northbridge/amd/amdk8/Config.lb
View File

@ -19,13 +19,13 @@ end
if HAVE_ACPI_TABLES
object amdk8_acpi.o
makerule ssdt.c
depends "$(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"
action "iasl -p $(PWD)/ssdt -tc $(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex"
action "mv ssdt.hex ssdt.c"
end
object ./ssdt.o
makerule ssdt.c
depends "$(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"
action "iasl -p $(PWD)/ssdt -tc $(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex"
action "mv ssdt.hex ssdt.c"
end
object ./ssdt.o
end

278
src/northbridge/amd/amdk8/amdk8_acpi.c
View File

@ -49,133 +49,131 @@ acknowledgement of AMD's proprietary rights in them.
unsigned long acpi_create_madt_lapics(unsigned long current)
{
device_t cpu;
int cpu_index = 0;
device_t cpu;
int cpu_index = 0;
for(cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
{
continue;
}
if (!cpu->enabled) {
continue;
}
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.u.apic.apic_id);
cpu_index++;
for(cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
{
continue;
}
if (!cpu->enabled) {
continue;
}
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.u.apic.apic_id);
cpu_index++;
}
}
return current;
return current;
}
unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint)
{
device_t cpu;
int cpu_index = 0;
device_t cpu;
int cpu_index = 0;
for(cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
{
continue;
}
if (!cpu->enabled) {
continue;
}
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint);
cpu_index++;
for(cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
{
continue;
}
if (!cpu->enabled) {
continue;
}
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint);
cpu_index++;
}
}
return current;
return current;
}
unsigned long acpi_create_srat_lapics(unsigned long current)
{
device_t cpu;
int cpu_index = 0;
device_t cpu;
int cpu_index = 0;
for(cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
{
continue;
}
if (!cpu->enabled) {
continue;
}
printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id);
current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id);
cpu_index++;
for(cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
{
continue;
}
if (!cpu->enabled) {
continue;
}
printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id);
current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id);
cpu_index++;
}
}
return current;
return current;
}
static unsigned long resk(uint64_t value)
{
unsigned long resultk;
if (value < (1ULL << 42)) {
resultk = value >> 10;
}
else {
resultk = 0xffffffff;
}
return resultk;
unsigned long resultk;
if (value < (1ULL << 42)) {
resultk = value >> 10;
}
else {
resultk = 0xffffffff;
}
return resultk;
}
struct acpi_srat_mem_state {
unsigned long current;
unsigned long current;
};
void set_srat_mem(void *gp, struct device *dev, struct resource *res)
{
struct acpi_srat_mem_state *state = gp;
unsigned long basek, sizek;
basek = resk(res->base);
sizek = resk(res->size);
struct acpi_srat_mem_state *state = gp;
unsigned long basek, sizek;
basek = resk(res->base);
sizek = resk(res->size);
printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n",
dev_path(dev), res->index, basek, sizek);
/*
0-640K must be on node 0
next range is from 1M---
So will cut off before 1M in the mem range
*/
if((basek+sizek)<1024) return;
printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n",
dev_path(dev), res->index, basek, sizek);
/*
0-640K must be on node 0
next range is from 1M---
So will cut off before 1M in the mem range
*/
if((basek+sizek)<1024) return;
if(basek<1024) {
sizek -= 1024 - basek;
basek = 1024;
}
if(basek<1024) {
sizek -= 1024 - basek;
basek = 1024;
}
state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); // need to figure out NV
state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); // need to figure out NV
}
unsigned long acpi_fill_srat(unsigned long current)
{
struct acpi_srat_mem_state srat_mem_state;
struct acpi_srat_mem_state srat_mem_state;
/* create all subtables for processors */
current = acpi_create_srat_lapics(current);
/* create all subtables for processors */
current = acpi_create_srat_lapics(current);
/* create all subteble for memory range */
/* create all subteble for memory range */
/* 0-640K must be on node 0 */
current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable
#if 1
srat_mem_state.current = current;
search_global_resources(
IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
set_srat_mem, &srat_mem_state);
/* 0-640K must be on node 0 */
current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable
current = srat_mem_state.current;
#endif
return current;
srat_mem_state.current = current;
search_global_resources(
IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
set_srat_mem, &srat_mem_state);
current = srat_mem_state.current;
return current;
}
@ -243,9 +241,9 @@ unsigned long acpi_fill_slit(unsigned long current)
}
}
current += 8+nodes*nodes;
current += 8+nodes*nodes;
return current;
return current;
}
@ -255,10 +253,10 @@ unsigned long acpi_fill_slit(unsigned long current)
// moved from mb acpi_tables.c
static void int_to_stream(uint32_t val, uint8_t *dest)
{
int i;
for(i=0;i<4;i++) {
*(dest+i) = (val >> (8*i)) & 0xff;
}
int i;
for(i=0;i<4;i++) {
*(dest+i) = (val >> (8*i)) & 0xff;
}
}
@ -266,60 +264,60 @@ static void int_to_stream(uint32_t val, uint8_t *dest)
void update_ssdt(void *ssdt)
{
uint8_t *BUSN;
uint8_t *MMIO;
uint8_t *PCIO;
uint8_t *SBLK;
uint8_t *TOM1;
uint8_t *SBDN;
uint8_t *HCLK;
uint8_t *HCDN;
uint8_t *BUSN;
uint8_t *MMIO;
uint8_t *PCIO;
uint8_t *SBLK;
uint8_t *TOM1;
uint8_t *SBDN;
uint8_t *HCLK;
uint8_t *HCDN;
uint8_t *CBST;
int i;
device_t dev;
uint32_t dword;
msr_t msr;
int i;
device_t dev;
uint32_t dword;
msr_t msr;
BUSN = ssdt+0x3a; //+5 will be next BUSN
MMIO = ssdt+0x57; //+5 will be next MMIO
PCIO = ssdt+0xaf; //+5 will be next PCIO
SBLK = ssdt+0xdc; // one byte
TOM1 = ssdt+0xe3; //
SBDN = ssdt+0xed;//
HCLK = ssdt+0xfa; //+5 will be next HCLK
HCDN = ssdt+0x12a; //+5 will be next HCDN
BUSN = ssdt+0x3a; //+5 will be next BUSN
MMIO = ssdt+0x57; //+5 will be next MMIO
PCIO = ssdt+0xaf; //+5 will be next PCIO
SBLK = ssdt+0xdc; // one byte
TOM1 = ssdt+0xe3; //
SBDN = ssdt+0xed; //
HCLK = ssdt+0xfa; //+5 will be next HCLK
HCDN = ssdt+0x12a; //+5 will be next HCDN
CBST = ssdt+0x157; //
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
for(i=0;i<4;i++) {
dword = pci_read_config32(dev, 0xe0+i*4);
int_to_stream(dword, BUSN+i*5);
}
for(i=0;i<0x10;i++) {
dword = pci_read_config32(dev, 0x80+i*4);
int_to_stream(dword, MMIO+i*5);
}
for(i=0;i<0x08;i++) {
dword = pci_read_config32(dev, 0xc0+i*4);
int_to_stream(dword, PCIO+i*5);
}
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
for(i=0;i<4;i++) {
dword = pci_read_config32(dev, 0xe0+i*4);
int_to_stream(dword, BUSN+i*5);
}
for(i=0;i<0x10;i++) {
dword = pci_read_config32(dev, 0x80+i*4);
int_to_stream(dword, MMIO+i*5);
}
for(i=0;i<0x08;i++) {
dword = pci_read_config32(dev, 0xc0+i*4);
int_to_stream(dword, PCIO+i*5);
}
*SBLK = (uint8_t)(sysconf.sblk);
*SBLK = (uint8_t)(sysconf.sblk);
msr = rdmsr(TOP_MEM);
int_to_stream(msr.lo, TOM1);
msr = rdmsr(TOP_MEM);
int_to_stream(msr.lo, TOM1);
for(i=0;i<sysconf.hc_possible_num;i++) {
int_to_stream(sysconf.pci1234[i], HCLK + i*5);
int_to_stream(sysconf.hcdn[i], HCDN + i*5);
}
for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
int_to_stream(0x00000000, HCLK + i*5);
int_to_stream(0x20202020, HCDN + i*5);
}
for(i=0;i<sysconf.hc_possible_num;i++) {
int_to_stream(sysconf.pci1234[i], HCLK + i*5);
int_to_stream(sysconf.hcdn[i], HCDN + i*5);
}
for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
int_to_stream(0x00000000, HCLK + i*5);
int_to_stream(0x20202020, HCDN + i*5);
}
int_to_stream(sysconf.sbdn, SBDN);
int_to_stream(sysconf.sbdn, SBDN);
if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0
*CBST = (uint8_t) (0x0f);

86
src/northbridge/amd/amdk8/amdk8_f.h
View File

@ -461,48 +461,48 @@ that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10,
//struct definitions
struct dimm_size {
uint8_t per_rank; // it is rows + col + bank_lines + data lines */
uint8_t rows;
uint8_t col;
uint8_t bank; //1, 2, 3 mean 2, 4, 8
uint8_t rank;
uint8_t per_rank; // it is rows + col + bank_lines + data lines */
uint8_t rows;
uint8_t col;
uint8_t bank; //1, 2, 3 mean 2, 4, 8
uint8_t rank;
} __attribute__((packed));
struct mem_info { // pernode
uint32_t dimm_mask;
struct dimm_size sz[DIMM_SOCKETS];
uint32_t x4_mask;
uint32_t x16_mask;
uint32_t dimm_mask;
struct dimm_size sz[DIMM_SOCKETS];
uint32_t x4_mask;
uint32_t x16_mask;
uint32_t single_rank_mask;
uint32_t page_1k_mask;
// uint32_t ecc_mask;
// uint32_t registered_mask;
uint8_t is_opteron;
uint8_t is_registered;
uint8_t is_ecc;
uint8_t is_Width128;
uint32_t page_1k_mask;
// uint32_t ecc_mask;
// uint32_t registered_mask;
uint8_t is_opteron;
uint8_t is_registered;
uint8_t is_ecc;
uint8_t is_Width128;
uint8_t is_64MuxMode;
uint8_t memclk_set; // we need to use this to retrieve the mem param
uint8_t memclk_set; // we need to use this to retrieve the mem param
uint8_t rsv[2];
} __attribute__((packed));
struct link_pair_st {
device_t udev;
uint32_t upos;
uint32_t uoffs;
device_t dev;
uint32_t pos;
uint32_t offs;
device_t udev;
uint32_t upos;
uint32_t uoffs;
device_t dev;
uint32_t pos;
uint32_t offs;
} __attribute__((packed));
struct sys_info {
uint8_t ctrl_present[NODE_NUMS];
struct mem_info meminfo[NODE_NUMS];
uint8_t ctrl_present[NODE_NUMS];
struct mem_info meminfo[NODE_NUMS];
struct mem_controller ctrl[NODE_NUMS];
uint8_t mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail
uint32_t tom_k;
uint32_t tom2_k;
uint32_t tom_k;
uint32_t tom2_k;
uint32_t mem_base[NODE_NUMS];
uint32_t cs_base[NODE_NUMS*8]; //8 cs_idx
@ -511,9 +511,9 @@ struct sys_info {
uint8_t dqs_delay_a[NODE_NUMS*2*2*9]; //8 node channel 2, direction 2 , bytelane *9
uint8_t dqs_rcvr_dly_a[NODE_NUMS*2*8]; //8 node, channel 2, receiver 8
uint32_t nodes;
struct link_pair_st link_pair[16];// enough? only in_conherent
uint32_t link_pair_num;
uint32_t ht_c_num;
struct link_pair_st link_pair[16];// enough? only in_conherent
uint32_t link_pair_num;
uint32_t ht_c_num;
uint32_t sbdn;
uint32_t sblk;
uint32_t sbbusn;
@ -526,38 +526,38 @@ static void soft_reset(void);
static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
{
int i;
uint32_t mask = 0;
int i;
uint32_t mask = 0;
unsigned needs_reset = 0;
if(sysinfo->nodes == 1) return; // in case only one cpu installed
for(i=1; i<sysinfo->nodes; i++) {
/* Skip everything if I don't have any memory on this controller */
if(sysinfo->mem_trained[i]==0x00) continue;
for(i=1; i<sysinfo->nodes; i++) {
/* Skip everything if I don't have any memory on this controller */
if(sysinfo->mem_trained[i]==0x00) continue;
mask |= (1<<i);
mask |= (1<<i);
}
}
i = 1;
while(1) {
i = 1;
while(1) {
if(mask & (1<<i)) {
if((sysinfo->mem_trained[i])!=0x80) {
mask &= ~(1<<i);
}
}
if(!mask) break;
if(!mask) break;
#if 0
/* cpu_relax */
__asm__ __volatile__("rep;nop": : :"memory");
#endif
i++;
i%=sysinfo->nodes;
i++;
i%=sysinfo->nodes;
}
for(i=0; i<sysinfo->nodes; i++) {
@ -566,7 +566,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
#else
printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
#endif
switch(sysinfo->mem_trained[i]) {
switch(sysinfo->mem_trained[i]) {
case 0: //don't need train
case 1: //trained
break;

42
src/northbridge/amd/amdk8/amdk8_f_pci.c
View File

@ -4,53 +4,53 @@
/* bit [10,8] are dev func, bit[1,0] are dev index */
static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32_t index)
{
uint32_t dword;
uint32_t dword;
pci_write_config32(dev, index_reg, index);
pci_write_config32(dev, index_reg, index);
dword = pci_read_config32(dev, index_reg+0x4);
dword = pci_read_config32(dev, index_reg+0x4);
return dword;
return dword;
}
static void pci_write_config32_index(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data)
{
pci_write_config32(dev, index_reg, index);
pci_write_config32(dev, index_reg, index);
pci_write_config32(dev, index_reg + 0x4, data);
pci_write_config32(dev, index_reg + 0x4, data);
}
static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index)
{
uint32_t dword;
uint32_t dword;
index &= ~(1<<30);
pci_write_config32(dev, index_reg, index);
index &= ~(1<<30);
pci_write_config32(dev, index_reg, index);
do {
dword = pci_read_config32(dev, index_reg);
} while (!(dword & (1<<31)));
do {
dword = pci_read_config32(dev, index_reg);
} while (!(dword & (1<<31)));
dword = pci_read_config32(dev, index_reg+0x4);
dword = pci_read_config32(dev, index_reg+0x4);
return dword;
return dword;
}
static void pci_write_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data)
{
uint32_t dword;
uint32_t dword;
pci_write_config32(dev, index_reg + 0x4, data);
pci_write_config32(dev, index_reg + 0x4, data);
index |= (1<<30);
pci_write_config32(dev, index_reg, index);
do {
dword = pci_read_config32(dev, index_reg);
} while (!(dword & (1<<31)));
index |= (1<<30);
pci_write_config32(dev, index_reg, index);
do {
dword = pci_read_config32(dev, index_reg);
} while (!(dword & (1<<31)));
}

410
src/northbridge/amd/amdk8/coherent_ht.c
View File

@ -105,7 +105,7 @@
#endif
#ifndef ENABLE_APIC_EXT_ID
#define ENABLE_APIC_EXT_ID 0
#define ENABLE_APIC_EXT_ID 0
#endif
@ -166,9 +166,9 @@ static void enable_apic_ext_id(u8 node)
u32 val;
val = pci_read_config32(NODE_HT(node), 0x68);
val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
pci_write_config32(NODE_HT(node), 0x68, val);
val = pci_read_config32(NODE_HT(node), 0x68);
val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
pci_write_config32(NODE_HT(node), 0x68, val);
#endif
}
@ -253,7 +253,7 @@ static void rename_temp_node(u8 node)
val=pci_read_config32(NODE_HT(7), 0x60);
val &= (~7); /* clear low bits. */
val |= node; /* new node */
val |= node; /* new node */
pci_write_config32(NODE_HT(7), 0x60, val);
print_spew(" done.\r\n");
@ -268,7 +268,7 @@ static int verify_connection(u8 dest)
* established and actually working by reading the
* remode node's vendor/device id
*/
val = pci_read_config32(NODE_HT(dest),0);
val = pci_read_config32(NODE_HT(dest),0);
if(val != 0x11001022)
return 0;
@ -378,27 +378,27 @@ static int optimize_connection(device_t node1, uint8_t link1, device_t node2, ui
static uint8_t get_linkn_first(uint8_t byte)
{
if(byte & 0x02) { byte = 0; }
else if(byte & 0x04) { byte = 1; }
else if(byte & 0x08) { byte = 2; }
return byte;
if(byte & 0x02) { byte = 0; }
else if(byte & 0x04) { byte = 1; }
else if(byte & 0x08) { byte = 2; }
return byte;
}
static uint8_t get_linkn_last(uint8_t byte)
{
if(byte & 0x02) { byte &= 0x0f; byte |= 0x00; }
if(byte & 0x04) { byte &= 0x0f; byte |= 0x10; }
if(byte & 0x08) { byte &= 0x0f; byte |= 0x20; }
return byte>>4;
if(byte & 0x02) { byte &= 0x0f; byte |= 0x00; }
if(byte & 0x04) { byte &= 0x0f; byte |= 0x10; }
if(byte & 0x08) { byte &= 0x0f; byte |= 0x20; }
return byte>>4;
}
static uint8_t get_linkn_last_count(uint8_t byte)
{
byte &= 0x0f;
if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; }
if(byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; }
if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; }
return byte>>4;
byte &= 0x0f;
if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; }
if(byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; }
if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; }
return byte>>4;
}
static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is for temp use*/
@ -454,25 +454,25 @@ static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) {
}
static void opt_broadcast_rt_group(const u8 *conn, int num) {
int i;
int i;
for(i=0; i<num; i+=3) {
opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]);
}
for(i=0; i<num; i+=3) {
opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]);
}
}
static void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout) {
uint32_t val;
val = get_row(source, dest);
val += link_connection(source, kickout)<<16;
fill_row(source, dest, val);
uint32_t val;
val = get_row(source, dest);
val += link_connection(source, kickout)<<16;
fill_row(source, dest, val);
}
static void opt_broadcast_rt_plus_group(const u8 *conn, int num) {
int i;
int i;
for(i=0; i<num; i+=3) {
opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]);
}
for(i=0; i<num; i+=3) {
opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]);
}
}
#endif
@ -864,37 +864,37 @@ static unsigned setup_smp4(void)
#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
/* set link from 3 to 5 before enable it*/
val = get_row(7,3);
byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1);
byte = get_linkn_last_count(byte);
if((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/
byte &= 3; /*bit [3,2] is count-2*/
print_linkn("(3,5) link=", byte);
setup_remote_row_direct(3, 5, byte);
val = get_row(7,3);
byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1);
byte = get_linkn_last_count(byte);
if((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/
byte &= 3; /*bit [3,2] is count-2*/
print_linkn("(3,5) link=", byte);
setup_remote_row_direct(3, 5, byte);
}
val = get_row(2,2);
byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
byte = get_linkn_last_count(byte);
val = get_row(2,2);
byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
byte = get_linkn_last_count(byte);
if((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/
byte &= 3; /* bit [3,2] is count-2*/
print_linkn("(2,4) link=", byte);
setup_row_direct(2, 4, byte);
if((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/
byte &= 3; /* bit [3,2] is count-2*/
print_linkn("(2,4) link=", byte);
setup_row_direct(2, 4, byte);
}
#endif
//Beside 3, 1 is set, We need to make sure 3, 5 is set already in case has three link in 3
#if !CROSS_BAR_47_56
static const u8 conn4_3[] = {
3,0,
};
static const u8 conn4_3[] = {
3,0,
};
#else
static const u8 conn4_3[] = {
3,0,1,1,
};
static const u8 conn4_3[] = {
3,0,1,1,
};
#endif
setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3));
setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3));
/* ready to enable RT for Node 3 */
rename_temp_node(3);
@ -902,15 +902,15 @@ static unsigned setup_smp4(void)
// beside 2, 0 is set, We need to make sure 2, 4 link is set already in case has three link in 2
#if !CROSS_BAR_47_56
static const u8 conn4_2[] = {
2,1,
};
static const u8 conn4_2[] = {
2,1,
};
#else
static const u8 conn4_2[] = {
2,1,0,1,
};
static const u8 conn4_2[] = {
2,1,0,1,
};
#endif
setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2));
setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2));
#if 0
/*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */
@ -936,24 +936,24 @@ static unsigned setup_smp6(void)
nodes=6;
/* Setup and check temporary connection from Node 0 to Node 4 through 2*/
val = get_row(2,2);
byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
byte = get_linkn_last_count(byte);
val = get_row(2,2);
byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
byte = get_linkn_last_count(byte);
if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/
nodes = 4;
return nodes;
}
if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/
nodes = 4;
return nodes;
}
/* Setup and check temporary connection from Node 0 to Node 5 through 1, 3*/
/* set link from 3 to 5 before enable it*/
val = get_row(3,3);
byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1);
byte = get_linkn_last_count(byte);
if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/
nodes = 4;
return nodes;
}
/* set link from 3 to 5 before enable it*/
val = get_row(3,3);
byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1);
byte = get_linkn_last_count(byte);
if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/
nodes = 4;
return nodes;
}
/* We found 6 nodes so far. Now setup all nodes for 6p */
#warning "FIXME we need to find out the correct gateway for 6p"
@ -1053,24 +1053,24 @@ static unsigned setup_smp6(void)
setup_remote_row_direct(5,4, byte);
//init 5, 7 here
val = get_row(7,5);
byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3);
byte = get_linkn_last_count(byte);
if((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/
byte &= 3; /*bit [3,2] is count-2*/
print_linkn("(5,7) link=", byte);
setup_remote_row_direct(5, 7, byte);
val = get_row(7,5);
byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3);
byte = get_linkn_last_count(byte);
if((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/
byte &= 3; /*bit [3,2] is count-2*/
print_linkn("(5,7) link=", byte);
setup_remote_row_direct(5, 7, byte);
}
//init 4,6 here
val = get_row(4,4);
byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
byte = get_linkn_last_count(byte);
val = get_row(4,4);
byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
byte = get_linkn_last_count(byte);
if((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/
byte &= 3; /* bit [3,2] is count-2*/
print_linkn("(4,6) link=", byte);
setup_row_direct(4, 6, byte);
if((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/
byte &= 3; /* bit [3,2] is count-2*/
print_linkn("(4,6) link=", byte);
setup_row_direct(4, 6, byte);
}
#endif
@ -1144,11 +1144,11 @@ static unsigned setup_smp8(void)
byte = ((val>>16) & 0xfe) - link_connection(4,2);
#else
byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
byte = get_linkn_last_count(byte); /* Max link to 6*/
if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/
nodes = 6;
return nodes;
}
byte = get_linkn_last_count(byte); /* Max link to 6*/
if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/
nodes = 6;
return nodes;
}
#endif
#if CROSS_BAR_47_56
@ -1169,13 +1169,13 @@ static unsigned setup_smp8(void)
#if !CROSS_BAR_47_56
/* Setup and check temporary connection from Node 0 to Node 7 through 1, 3, 5*/
val = get_row(5,5);
byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3);
byte = get_linkn_last_count(byte);
if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/
nodes = 6;
return nodes;
}
val = get_row(5,5);
byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3);
byte = get_linkn_last_count(byte);
if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/
nodes = 6;
return nodes;
}
#endif
/* We found 8 nodes so far. Now setup all nodes for 8p */
@ -1230,53 +1230,53 @@ static unsigned setup_smp8(void)
#if CROSS_BAR_47_56
//init 5, 6 here
/* here init 5, 6 */
/* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/
val = get_row(5,5);
byte = ((val>>16) & 0xfe) - link_connection(5,3);
/* here init 5, 6 */
/* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/
val = get_row(5,5);
byte = ((val>>16) & 0xfe) - link_connection(5,3);
#if TRY_HIGH_FIRST == 1
byte = get_linkn_first(byte);
#else
byte = get_linkn_last(byte);
byte = get_linkn_last(byte);
#endif
print_linkn("(5,6) link=", byte);
setup_row_direct(5, 6, byte);
print_linkn("(5,6) link=", byte);
setup_row_direct(5, 6, byte);
setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
for(byte=0; byte<4; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
for(byte=0; byte<4; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
setup_temp_row(5,6);
verify_connection(7);
verify_connection(7);
val = get_row(7,6); // to chect it if it is node6 before renaming
if( (val>>16) == 1) { // it is real node 7 so swap it
/* We need to recompute link to 6 */
val = get_row(5,5);
byte = ((val>>16) & 0xfe) - link_connection(5,3);
/* We need to recompute link to 6 */
val = get_row(5,5);
byte = ((val>>16) & 0xfe) - link_connection(5,3);
#if TRY_HIGH_FIRST == 1
byte = get_linkn_first(byte);
byte = get_linkn_first(byte);
#else
byte = get_linkn_last(byte);
byte = get_linkn_last(byte);
#endif
print_linkn("\t-->(5,6) link=", byte);
setup_row_direct(5, 6, byte);
print_linkn("\t-->(5,6) link=", byte);
setup_row_direct(5, 6, byte);
#if 0
setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
for(byte=0; byte<4; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
for(byte=0; byte<4; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
#endif
setup_temp_row(5,6);
verify_connection(7);
verify_connection(7);
}
val = pci_read_config32(NODE_HT(7), 0x6c);
byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
print_linkn("(6,5) link=", byte);
setup_remote_row_direct(6, 5, byte);
/*Till now 56, 65 done */
val = pci_read_config32(NODE_HT(7), 0x6c);
byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
print_linkn("(6,5) link=", byte);
setup_remote_row_direct(6, 5, byte);
/*Till now 56, 65 done */
#endif
rename_temp_node(6);
@ -1297,18 +1297,18 @@ static unsigned setup_smp8(void)
setup_remote_row_direct(7, 5, byte);
#else
val = get_row(4,4);
byte = ((val>>16) & 0xfe) - link_connection(4,2) - link_connection(4,6);
byte = get_linkn_first(byte);
print_linkn("(4,7) link=", byte);
setup_row_direct(4, 7, byte);
val = get_row(4,4);
byte = ((val>>16) & 0xfe) - link_connection(4,2) - link_connection(4,6);
byte = get_linkn_first(byte);
print_linkn("(4,7) link=", byte);
setup_row_direct(4, 7, byte);
/* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/
/* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/
for(byte=0; byte<4; byte+=2) {
setup_temp_row(byte,byte+2);
}
verify_connection(7);
verify_connection(7);
val = pci_read_config32(NODE_HT(7), 0x6c);
byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
@ -1386,25 +1386,25 @@ static unsigned setup_smp8(void)
#else
4, 5, 6, 1,
5, 4, 7, 1,
4, 5, 6, 1,
5, 4, 7, 1,
6, 1, 5, 0, // or 4, 1
6, 2, 4, 0,
6, 3, 5, 0, // or 4, 1
6, 1, 5, 0, // or 4, 1
6, 2, 4, 0,
6, 3, 5, 0, // or 4, 1
7, 0, 4, 0, // or 5, 1
7, 1, 5, 0,
7, 2, 4, 0, // or 5, 1
7, 3, 5, 0,
7, 0, 4, 0, // or 5, 1
7, 1, 5, 0,
7, 2, 4, 0, // or 5, 1
7, 3, 5, 0,
0, 7, 2, 0, /* restore it*/
1, 7, 3, 0,
2, 7, 4, 1,
3, 7, 5, 0,
2, 5, 4, 1, /* reset it */
3, 4, 5, 1,
2, 5, 4, 1, /* reset it */
3, 4, 5, 1,
4, 1, 2, 1, /* reset it */
4, 3, 2, 1,
@ -1418,12 +1418,12 @@ static unsigned setup_smp8(void)
setup_row_indirect_group(conn8_3, ARRAY_SIZE(conn8_3));
#if CROSS_BAR_47_56
/* for 47, 56, 57, 75, 46, 64 we need to substract another link to
6, 7, 6, 6, 7, 7 */
static const u8 conn8_4[] = {
/* for 47, 56, 57, 75, 46, 64 we need to substract another link to
6, 7, 6, 6, 7, 7 */
static const u8 conn8_4[] = {
//direct
4, 7, 6,
5, 6, 7,
4, 7, 6,
5, 6, 7,
5, 7, 6,
7, 5, 6,
4, 6, 7,
@ -1454,17 +1454,17 @@ static unsigned setup_smp8(void)
7, 2, 6, // needed for via 4
7, 2, 5, //???
7, 3, 6,
};
};
opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4));
opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4));
static const u8 conn8_5[] = {
2, 7, 0,
static const u8 conn8_5[] = {
2, 7, 0,
3, 6, 1,
};
3, 6, 1,
};
opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5));
opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5));
#endif
@ -1745,70 +1745,70 @@ static int optimize_link_read_pointers(unsigned nodes)
static inline unsigned get_nodes(void)
{
return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
}
static int optimize_link_coherent_ht(void)
{
int needs_reset = 0;
int needs_reset = 0;
unsigned nodes;
unsigned nodes;
nodes = get_nodes();
nodes = get_nodes();
#if CONFIG_MAX_PHYSICAL_CPUS > 1
if(nodes>1) {
needs_reset |= optimize_connection(
NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
}
if(nodes>1) {
needs_reset |= optimize_connection(
NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
}
#if CONFIG_MAX_PHYSICAL_CPUS > 2
if(nodes>2) {
/* optimize physical connections - by LYH */
static const u8 opt_conn4[] = {
0,2,
1,3,
2,3,
};
needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4));
}
if(nodes>2) {
/* optimize physical connections - by LYH */
static const u8 opt_conn4[] = {
0,2,
1,3,
2,3,
};
needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4));
}
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 4
if(nodes>4) {
static const uint8_t opt_conn6[] ={
2, 4,
3, 5,
#if !CROSS_BAR_47_56
4, 5,
#endif
};
needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6));
}
if(nodes>4) {
static const uint8_t opt_conn6[] ={
2, 4,
3, 5,
#if !CROSS_BAR_47_56
4, 5,
#endif
};
needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6));
}
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 6
if(nodes>6) {
static const uint8_t opt_conn8[] ={
4, 6,
#if CROSS_BAR_47_56
4, 7,
5, 6,
#endif
5, 7,
6, 7,
};
needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8));
}
if(nodes>6) {
static const uint8_t opt_conn8[] ={
4, 6,
#if CROSS_BAR_47_56
4, 7,
5, 6,
#endif
5, 7,
6, 7,
};
needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8));
}
#endif
#endif
needs_reset |= apply_cpu_errata_fixes(nodes);
needs_reset |= optimize_link_read_pointers(nodes);
needs_reset |= apply_cpu_errata_fixes(nodes);
needs_reset |= optimize_link_read_pointers(nodes);
return needs_reset;
return needs_reset;
}
#if RAMINIT_SYSINFO == 1
@ -1823,9 +1823,9 @@ static int setup_coherent_ht_domain(void)
enable_bsp_routing();
#if CONFIG_MAX_PHYSICAL_CPUS > 1
nodes = setup_smp();
nodes = verify_mp_capabilities(nodes);
clear_dead_routes(nodes);
nodes = setup_smp();
nodes = verify_mp_capabilities(nodes);
clear_dead_routes(nodes);
#endif
if (nodes == 1) {

180
src/northbridge/amd/amdk8/debug.c
View File

@ -7,10 +7,10 @@ static inline void print_debug_addr(const char *str, void *val)
{
#if CACHE_AS_RAM_ADDRESS_DEBUG == 1
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("------Address debug: %s%x------\r\n", str, val);
#else
printk_debug("------Address debug: %s%x------\r\n", str, val);
#else
print_debug ("------Address debug: "); print_debug(str); print_debug_hex32(val); print_debug("------\r\n");
#endif
#endif
#endif
}
@ -69,7 +69,7 @@ static void dump_pci_device(unsigned dev)
unsigned char val;
if ((i & 0x0f) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("\r\n%02x:",i);
printk_debug("\r\n%02x:",i);
#else
print_debug("\r\n");
print_debug_hex8(i);
@ -91,32 +91,32 @@ static void dump_pci_device(unsigned dev)
static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index);
static void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
{
int i;
print_debug_pci_dev(dev);
int i;
print_debug_pci_dev(dev);
print_debug(" -- index_reg="); print_debug_hex32(index_reg);
for(i = 0; i < 0x40; i++) {
uint32_t val;
for(i = 0; i < 0x40; i++) {
uint32_t val;
int j;
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("\r\n%02x:",i);
printk_debug("\r\n%02x:",i);
#else
print_debug("\r\n");
print_debug_hex8(i);
print_debug_char(':');
print_debug("\r\n");
print_debug_hex8(i);
print_debug_char(':');
#endif
val = pci_read_config32_index_wait(dev, index_reg, i);
val = pci_read_config32_index_wait(dev, index_reg, i);
for(j=0;j<4;j++) {
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug(" %02x", val & 0xff);
printk_debug(" %02x", val & 0xff);
#else
print_debug_char(' '); print_debug_hex8(val&0xff);
print_debug_char(' '); print_debug_hex8(val&0xff);
#endif
val >>= 8;
}
}
print_debug("\r\n");
}
print_debug("\r\n");
}
#endif
@ -135,39 +135,39 @@ static void dump_pci_devices(void)
}
dump_pci_device(dev);
if(((dev>>12) & 0x07) == 0) {
uint8_t hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
if((hdr_type & 0x80) != 0x80) {
dev += PCI_DEV(0,0,7);
}
}
if(((dev>>12) & 0x07) == 0) {
uint8_t hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
if((hdr_type & 0x80) != 0x80) {
dev += PCI_DEV(0,0,7);
}
}
}
}
static void dump_pci_devices_on_bus(unsigned busn)
{
device_t dev;
for(dev = PCI_DEV(busn, 0, 0);
dev <= PCI_DEV(busn, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0x0000)) {
continue;
}
dump_pci_device(dev);
device_t dev;
for(dev = PCI_DEV(busn, 0, 0);
dev <= PCI_DEV(busn, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0x0000)) {
continue;
}
dump_pci_device(dev);
if(((dev>>12) & 0x07) == 0) {
uint8_t hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
if((hdr_type & 0x80) != 0x80) {
dev += PCI_DEV(0,0,7);
}
}
}
if(((dev>>12) & 0x07) == 0) {
uint8_t hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
if((hdr_type & 0x80) != 0x80) {
dev += PCI_DEV(0,0,7);
}
}
}
}
#ifndef DEBUG_SMBUS
@ -222,7 +222,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
if (device) {
int j;
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("dimm: %02x.1: %02x", i, device);
printk_debug("dimm: %02x.1: %02x", i, device);
#else
print_debug("dimm: ");
print_debug_hex8(i);
@ -234,7 +234,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
unsigned char byte;
if ((j & 0xf) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("\r\n%02x: ", j);
printk_debug("\r\n%02x: ", j);
#else
print_debug("\r\n");
print_debug_hex8(j);
@ -247,7 +247,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
}
byte = status & 0xff;
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%02x ", byte);
printk_debug("%02x ", byte);
#else
print_debug_hex8(byte);
print_debug_char(' ');
@ -260,41 +260,41 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
static void dump_smbus_registers(void)
{
unsigned device;
print_debug("\r\n");
for(device = 1; device < 0x80; device++) {
int j;
print_debug("\r\n");
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("smbus: %02x", device);
#else
print_debug("smbus: ");
print_debug_hex8(device);
print_debug("smbus: ");
print_debug_hex8(device);
#endif
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
status = smbus_read_byte(device, j);
if (status < 0) {
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
status = smbus_read_byte(device, j);
if (status < 0) {
break;
}
if ((j & 0xf) == 0) {
}
if ((j & 0xf) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("\r\n%02x: ",j);
#else
print_debug("\r\n");
print_debug_hex8(j);
print_debug(": ");
print_debug("\r\n");
print_debug_hex8(j);
print_debug(": ");
#endif
}
byte = status & 0xff;
}
byte = status & 0xff;
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%02x ", byte);
printk_debug("%02x ", byte);
#else
print_debug_hex8(byte);
print_debug_char(' ');
print_debug_hex8(byte);
print_debug_char(' ');
#endif
}
print_debug("\r\n");
}
print_debug("\r\n");
}
}
#endif
@ -303,42 +303,42 @@ static void dump_io_resources(unsigned port)
{
int i;
udelay(2000);
udelay(2000);
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%04x:\r\n", port);
#else
print_debug_hex16(port);
print_debug(":\r\n");
print_debug_hex16(port);
print_debug(":\r\n");
#endif
for(i=0;i<256;i++) {
uint8_t val;
if ((i & 0x0f) == 0) {
for(i=0;i<256;i++) {
uint8_t val;
if ((i & 0x0f) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%02x:", i);
#else
print_debug_hex8(i);
print_debug_char(':');
print_debug_hex8(i);
print_debug_char(':');
#endif
}
val = inb(port);
}
val = inb(port);
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug(" %02x",val);
#else
print_debug_char(' ');
print_debug_hex8(val);
print_debug_char(' ');
print_debug_hex8(val);
#endif
if ((i & 0x0f) == 0x0f) {
print_debug("\r\n");
}
if ((i & 0x0f) == 0x0f) {
print_debug("\r\n");
}
port++;
}
}
}
static void dump_mem(unsigned start, unsigned end)
{
unsigned i;
unsigned i;
print_debug("dump_mem:");
for(i=start;i<end;i++) {
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("\r\n%08x:", i);
@ -352,9 +352,9 @@ static void dump_mem(unsigned start, unsigned end)
printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
#else
print_debug(" ");
print_debug_hex8((unsigned char)*((unsigned char *)i));
print_debug_hex8((unsigned char)*((unsigned char *)i));
#endif
}
print_debug("\r\n");
}
print_debug("\r\n");
}
#endif

4
src/northbridge/amd/amdk8/early_ht.c
View File

@ -131,8 +131,8 @@ out:
uint16_t flags;
dev = PCI_DEV(0,real_last_unitid, 0);
flags = pci_read_config16(dev, real_last_pos + PCI_CAP_FLAGS);
flags &= ~0x1f;
flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
flags &= ~0x1f;
flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
pci_write_config16(dev, real_last_pos + PCI_CAP_FLAGS, flags);
}
#endif

144
src/northbridge/amd/amdk8/get_sblk_pci1234.c
View File

@ -35,36 +35,36 @@
#if 0
unsigned node_link_to_bus(unsigned node, unsigned link)
{
device_t dev;
unsigned reg;
device_t dev;
unsigned reg;
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
if (!dev) {
return 0;
}
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
uint32_t config_map;
unsigned dst_node;
unsigned dst_link;
unsigned bus_base;
config_map = pci_read_config32(dev, reg);
if ((config_map & 3) != 3) {
continue;
}
dst_node = (config_map >> 4) & 7;
dst_link = (config_map >> 8) & 3;
bus_base = (config_map >> 16) & 0xff;
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
if (!dev) {
return 0;
}
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
uint32_t config_map;
unsigned dst_node;
unsigned dst_link;
unsigned bus_base;
config_map = pci_read_config32(dev, reg);
if ((config_map & 3) != 3) {
continue;
}
dst_node = (config_map >> 4) & 7;
dst_link = (config_map >> 8) & 3;
bus_base = (config_map >> 16) & 0xff;
#if 0
printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
dst_node, dst_link, bus_base,
reg, config_map);
printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
dst_node, dst_link, bus_base,
reg, config_map);
#endif
if ((dst_node == node) && (dst_link == link))
{
return bus_base;
}
}
return 0;
if ((dst_node == node) && (dst_link == link))
{
return bus_base;
}
}
return 0;
}
#endif
@ -187,28 +187,28 @@ unsigned node_link_to_bus(unsigned node, unsigned link)
void get_sblk_pci1234(void)
{
device_t dev;
int i,j;
uint32_t dword;
device_t dev;
int i,j;
uint32_t dword;
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
dword = pci_read_config32(dev, 0x64);
sysconf.sblk = (dword>>8) & 0x3;
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
dword = pci_read_config32(dev, 0x64);
sysconf.sblk = (dword>>8) & 0x3;
dword &=0x0300;
dword |= 1;
sysconf.pci1234[0] = dword;
dword &=0x0300;
dword |= 1;
sysconf.pci1234[0] = dword;
sysconf.hcid[0] = 0;
/* About hardcoded numbering for HT_IO support
/* About hardcoded numbering for HT_IO support
*
* Set the node_id and link_id that could have a HT chain in the one
* array, (FIXME: which one?) then check if is enabled. Then update
* final value
*/
*/
/* Here we need to set hcdn
/* Here we need to set hcdn
*
* 1. hypertransport.c needs to record hcdn_reg together with 0xe0,
* 0xe4, 0xe8, 0xec when are set (FIXME: when WHAT is set?)
@ -216,48 +216,48 @@ void get_sblk_pci1234(void)
* 2. So at the same time we need update hcdn with hcdn_reg here. FIXME: Why?
*/
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
for(j=0;j<4;j++) {
uint32_t dwordx;
dwordx = pci_read_config32(dev, 0xe0 + j*4);
dwordx &=0xffff0ff1; /* keep bus num, node_id, link_num, enable bits */
if((dwordx & 0xff1) == dword) { /* SBLINK */
sysconf.pci1234[0] = dwordx;
for(j=0;j<4;j++) {
uint32_t dwordx;
dwordx = pci_read_config32(dev, 0xe0 + j*4);
dwordx &=0xffff0ff1; /* keep bus num, node_id, link_num, enable bits */
if((dwordx & 0xff1) == dword) { /* SBLINK */
sysconf.pci1234[0] = dwordx;
sysconf.hcdn[0] = sysconf.hcdn_reg[j];
continue;
}
continue;
}
if((dwordx & 1) == 1) {
/* We need to find out the number of HC
* for exact match
if((dwordx & 1) == 1) {
/* We need to find out the number of HC
* for exact match
*/
for(i=1;i<sysconf.hc_possible_num;i++) {
if((dwordx & 0xff0) == (sysconf.pci1234[i] & 0xff0)) {
sysconf.pci1234[i] = dwordx;
for(i=1;i<sysconf.hc_possible_num;i++) {
if((dwordx & 0xff0) == (sysconf.pci1234[i] & 0xff0)) {
sysconf.pci1234[i] = dwordx;
sysconf.hcdn[i] = sysconf.hcdn_reg[j];
break;
}
}
break;
}
}
/* For 0xff0 match or same node */
for(i=1;i<sysconf.hc_possible_num;i++) {
if((dwordx & 0xff0) == (dwordx & sysconf.pci1234[i] & 0xff0)) {
sysconf.pci1234[i] = dwordx;
/* For 0xff0 match or same node */
for(i=1;i<sysconf.hc_possible_num;i++) {
if((dwordx & 0xff0) == (dwordx & sysconf.pci1234[i] & 0xff0)) {
sysconf.pci1234[i] = dwordx;
sysconf.hcdn[i] = sysconf.hcdn_reg[j];
break;
}
}
}
}
break;
}
}
}
}
for(i=1;i<sysconf.hc_possible_num;i++) {
if((sysconf.pci1234[i] & 1) != 1) {
sysconf.pci1234[i] = 0;
for(i=1;i<sysconf.hc_possible_num;i++) {
if((sysconf.pci1234[i] & 1) != 1) {
sysconf.pci1234[i] = 0;
sysconf.hcdn[i] = 0x20202020;
}
}
sysconf.hcid[i] = 0;
}
}
}

463
src/northbridge/amd/amdk8/incoherent_ht.c
View File

@ -8,7 +8,7 @@
#include <device/hypertransport_def.h>
#ifndef K8_HT_FREQ_1G_SUPPORT
#define K8_HT_FREQ_1G_SUPPORT 0
#define K8_HT_FREQ_1G_SUPPORT 0
#endif
#ifndef K8_SCAN_PCI_BUS
@ -16,20 +16,20 @@
#endif
#ifndef K8_ALLOCATE_IO_RANGE
#define K8_ALLOCATE_IO_RANGE 0
#define K8_ALLOCATE_IO_RANGE 0
#endif
// Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM
#ifndef K8_ALLOCATE_MMIO_RANGE
#define K8_ALLOCATE_MMIO_RANGE 0
#define K8_ALLOCATE_MMIO_RANGE 0
#endif
static inline void print_linkn_in (const char *strval, uint8_t byteval)
{
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%s%02x\r\n", strval, byteval);
printk_debug("%s%02x\r\n", strval, byteval);
#else
print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
#endif
}
@ -73,7 +73,7 @@ static uint8_t ht_lookup_slave_capability(device_t dev)
static uint8_t ht_lookup_host_capability(device_t dev)
{
return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format
return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format
}
static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid)
@ -91,11 +91,11 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid
/* Check if is already collapsed */
if((!offset_unitid) || (offset_unitid && (!((HT_CHAIN_END_UNITID_BASE == 0) && (HT_CHAIN_END_UNITID_BASE <HT_CHAIN_UNITID_BASE))))) {
dev = PCI_DEV(bus, 0, 0);
id = pci_read_config32(dev, PCI_VENDOR_ID);
if ( ! ( (id == 0xffffffff) || (id == 0x00000000) ||
(id == 0x0000ffff) || (id == 0xffff0000) ) ) {
return;
}
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (!((id == 0xffffffff) || (id == 0x00000000) ||
(id == 0x0000ffff) || (id == 0xffff0000))) {
return;
}
}
/* Spin through the devices and collapse any previous
@ -151,17 +151,18 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos)
if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
#if K8_HT_FREQ_1G_SUPPORT == 1
#if K8_REV_F_SUPPORT == 0
if (is_cpu_pre_e0()) { // only E0 later support 1GHz
if (is_cpu_pre_e0()) { // only E0 later support 1GHz
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
}
#endif
#else
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
#endif
}
return freq_cap;
}
static uint8_t ht_read_width_cap(device_t dev, uint8_t pos)
{
uint8_t width_cap = pci_read_config8(dev, pos);
@ -180,8 +181,9 @@ static uint8_t ht_read_width_cap(device_t dev, uint8_t pos)
return width_cap;
}
#define LINK_OFFS(CTRL, WIDTH,FREQ,FREQ_CAP) \
(((CTRL & 0xff) << 24) | ((WIDTH & 0xff) << 16) | ((FREQ & 0xff) << 8) | (FREQ_CAP & 0xFF))
(((CTRL & 0xff) << 24) | ((WIDTH & 0xff) << 16) | ((FREQ & 0xff) << 8) | (FREQ_CAP & 0xFF))
#define LINK_CTRL(OFFS) ((OFFS >> 24) & 0xFF)
#define LINK_WIDTH(OFFS) ((OFFS >> 16) & 0xFF)
@ -189,19 +191,19 @@ static uint8_t ht_read_width_cap(device_t dev, uint8_t pos)
#define LINK_FREQ_CAP(OFFS) ((OFFS) & 0xFF)
#define PCI_HT_HOST_OFFS LINK_OFFS( \
PCI_HT_CAP_HOST_CTRL, \
PCI_HT_CAP_HOST_CTRL, \
PCI_HT_CAP_HOST_WIDTH, \
PCI_HT_CAP_HOST_FREQ, \
PCI_HT_CAP_HOST_FREQ_CAP)
#define PCI_HT_SLAVE0_OFFS LINK_OFFS( \
PCI_HT_CAP_SLAVE_CTRL0, \
PCI_HT_CAP_SLAVE_CTRL0, \
PCI_HT_CAP_SLAVE_WIDTH0, \
PCI_HT_CAP_SLAVE_FREQ0, \
PCI_HT_CAP_SLAVE_FREQ_CAP0)
#define PCI_HT_SLAVE1_OFFS LINK_OFFS( \
PCI_HT_CAP_SLAVE_CTRL1, \
PCI_HT_CAP_SLAVE_CTRL1, \
PCI_HT_CAP_SLAVE_WIDTH1, \
PCI_HT_CAP_SLAVE_FREQ1, \
PCI_HT_CAP_SLAVE_FREQ_CAP1)
@ -280,6 +282,7 @@ static int ht_optimize_link(
return needs_reset;
}
#if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1)
#if RAMINIT_SYSINFO == 1
@ -290,12 +293,12 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
static int scan_pci_bus( unsigned bus)
#endif
{
/*
here we already can access PCI_DEV(bus, 0, 0) to PCI_DEV(bus, 0x1f, 0x7)
So We can scan these devices to find out if they are bridge
If it is pci bridge, We need to set busn in bridge, and go on
For ht bridge, We need to set the busn in bridge and ht_setup_chainx, and the scan_pci_bus
*/
/*
here we already can access PCI_DEV(bus, 0, 0) to PCI_DEV(bus, 0x1f, 0x7)
So We can scan these devices to find out if they are bridge
If it is pci bridge, We need to set busn in bridge, and go on
For ht bridge, We need to set the busn in bridge and ht_setup_chainx, and the scan_pci_bus
*/
unsigned int devfn;
unsigned new_bus;
unsigned max_bus;
@ -315,52 +318,52 @@ static int scan_pci_bus( unsigned bus)
new_bus = bus;
for (devfn = 0; devfn <= 0xff; devfn++) {
uint8_t hdr_type;
uint16_t class;
uint8_t hdr_type;
uint16_t class;
uint32_t buses;
device_t dev;
uint16_t cr;
dev = PCI_DEV((bus & 0xff), ((devfn>>3) & 0x1f), (devfn & 0x7));
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
class = pci_read_config16(dev, PCI_CLASS_DEVICE);
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
class = pci_read_config16(dev, PCI_CLASS_DEVICE);
switch(hdr_type & 0x7f) { /* header type */
case PCI_HEADER_TYPE_BRIDGE:
if (class != PCI_CLASS_BRIDGE_PCI) goto bad;
case PCI_HEADER_TYPE_BRIDGE:
if (class != PCI_CLASS_BRIDGE_PCI) goto bad;
/* set the bus range dev */
/* Clear all status bits and turn off memory, I/O and master enables. */
cr = pci_read_config16(dev, PCI_COMMAND);
pci_write_config16(dev, PCI_COMMAND, 0x0000);
pci_write_config16(dev, PCI_STATUS, 0xffff);
/* Clear all status bits and turn off memory, I/O and master enables. */
cr = pci_read_config16(dev, PCI_COMMAND);
pci_write_config16(dev, PCI_COMMAND, 0x0000);
pci_write_config16(dev, PCI_STATUS, 0xffff);
buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
buses &= 0xff000000;
buses &= 0xff000000;
new_bus++;
buses |= (((unsigned int) (bus & 0xff) << 0) |
((unsigned int) (new_bus & 0xff) << 8) |
((unsigned int) max_bus << 16));
pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
buses |= (((unsigned int) (bus & 0xff) << 0) |
((unsigned int) (new_bus & 0xff) << 8) |
((unsigned int) max_bus << 16));
pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
/* here we need to figure out if dev is a ht bridge
if it is ht bridge, we need to call ht_setup_chainx at first
Not verified --- yhlu
Not verified --- yhlu
*/
uint8_t upos;
upos = ht_lookup_host_capability(dev); // one func one ht sub
if (upos) { // sub ht chain
upos = ht_lookup_host_capability(dev); // one func one ht sub
if (upos) { // sub ht chain
uint8_t busn;
busn = (new_bus & 0xff);
/* Make certain the HT bus is not enumerated */
ht_collapse_previous_enumeration(busn, 0);
/* Make certain the HT bus is not enumerated */
ht_collapse_previous_enumeration(busn, 0);
/* scan the ht chain */
#if RAMINIT_SYSINFO == 1
ht_setup_chainx(dev,upos,busn, 0, sysinfo); // don't need offset unitid
ht_setup_chainx(dev,upos,busn, 0, sysinfo); // don't need offset unitid
#else
new_bus |= (ht_setup_chainx(dev, upos, busn, 0)<<16); // store reset_needed to upword
#endif
}
}
#if RAMINIT_SYSINFO == 1
new_bus = scan_pci_bus(new_bus, sysinfo);
@ -369,28 +372,28 @@ static int scan_pci_bus( unsigned bus)
#endif
/* set real max bus num in that */
buses = (buses & 0xff00ffff) |
((unsigned int) (new_bus & 0xff) << 16);
pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
buses = (buses & 0xff00ffff) |
((unsigned int) (new_bus & 0xff) << 16);
pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
pci_write_config16(dev, PCI_COMMAND, cr);
break;
default:
bad:
break;
default:
bad:
;
}
}
/* if this is not a multi function device,
* or the device is not present don't waste
* time probing another function.
* Skip to next device.
*/
if ( ((devfn & 0x07) == 0x00) && ((hdr_type & 0x80) != 0x80))
{
devfn += 0x07;
}
}
/* if this is not a multi function device,
* or the device is not present don't waste
* time probing another function.
* Skip to next device.
*/
if ( ((devfn & 0x07) == 0x00) && ((hdr_type & 0x80) != 0x80))
{
devfn += 0x07;
}
}
return new_bus;
}
@ -412,9 +415,9 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
#endif
#if HT_CHAIN_END_UNITID_BASE != 0x20
//let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE
unsigned real_last_unitid;
uint8_t real_last_pos;
//let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE
unsigned real_last_unitid;
uint8_t real_last_pos;
int ht_dev_num = 0;
uint8_t end_used = 0;
#endif
@ -438,20 +441,20 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
}
if (ctrl & ((1 << 4) | (1 << 8))) {
/*
* Either the link has failed, or we have
* a CRC error.
* Sometimes this can happen due to link
* retrain, so lets knock it down and see
* if its transient
*/
/*
* Either the link has failed, or we have
* a CRC error.
* Sometimes this can happen due to link
* retrain, so lets knock it down and see
* if its transient
*/
ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
pci_write_config16(udev, upos + LINK_CTRL(uoffs), ctrl);
ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs));
if (ctrl & ((1 << 4) | (1 << 8))) {
print_err("Detected error on Hypertransport Link\n");
pci_write_config16(udev, upos + LINK_CTRL(uoffs), ctrl);
ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs));
if (ctrl & ((1 << 4) | (1 << 8))) {
print_err("Detected error on Hypertransport Link\n");
break;
}
}
}
} while((ctrl & (1 << 5)) == 0);
@ -461,17 +464,17 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
id = pci_read_config32(dev, PCI_VENDOR_ID);
/* If the chain is enumerated quit */
if ( (id == 0xffffffff) || (id == 0x00000000) ||
(id == 0x0000ffff) || (id == 0xffff0000))
if ((id == 0xffffffff) || (id == 0x00000000) ||
(id == 0x0000ffff) || (id == 0xffff0000))
{
break;
}
pos = ht_lookup_slave_capability(dev);
if (!pos) {
print_err("udev="); print_err_hex32(udev);
print_err("\tupos="); print_err_hex32(upos);
print_err("\tuoffs="); print_err_hex32(uoffs);
print_err("udev="); print_err_hex32(udev);
print_err("\tupos="); print_err_hex32(upos);
print_err("\tuoffs="); print_err_hex32(uoffs);
print_err("\tHT link capability not found\r\n");
break;
}
@ -481,14 +484,14 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
if(offset_unitid) {
if(next_unitid>= (bus ? 0x20:0x18) ) {
if(!end_used) {
next_unitid = HT_CHAIN_END_UNITID_BASE;
next_unitid = HT_CHAIN_END_UNITID_BASE;
end_used = 1;
} else {
goto out;
}
}
real_last_pos = pos;
real_last_pos = pos;
real_last_unitid = next_unitid;
ht_dev_num++;
}
@ -499,23 +502,23 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
flags |= next_unitid & 0x1f;
pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
/* Compute the number of unitids consumed */
count = (flags >> 5) & 0x1f;
/* Compute the number of unitids consumed */
count = (flags >> 5) & 0x1f;
/* Note the change in device number */
dev = PCI_DEV(bus, next_unitid, 0);
next_unitid += count;
next_unitid += count;
/* Find which side of the ht link we are on,
* by reading which direction our last write to PCI_CAP_FLAGS
* came from.
*/
flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;
offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;
#if RAMINIT_SYSINFO == 1
/* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */
/* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */
{
struct link_pair_st *link_pair = &sysinfo->link_pair[sysinfo->link_pair_num];
link_pair->udev = udev;
@ -541,30 +544,30 @@ out:
end_of_chain: ;
#if HT_CHAIN_END_UNITID_BASE != 0x20
if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used ) {
uint16_t flags;
if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used ) {
uint16_t flags;
int i;
flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
flags &= ~0x1f;
flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
flags &= ~0x1f;
flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
#if RAMINIT_SYSINFO == 1
#if RAMINIT_SYSINFO == 1
// Here need to change the dev in the array
for(i=0;i<sysinfo->link_pair_num;i++)
{
struct link_pair_st *link_pair = &sysinfo->link_pair[i];
if(link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) {
{
struct link_pair_st *link_pair = &sysinfo->link_pair[i];
if(link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) {
link_pair->udev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0);
continue;
}
if(link_pair->dev == PCI_DEV(bus, real_last_unitid, 0)) {
link_pair->dev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0);
}
}
if(link_pair->dev == PCI_DEV(bus, real_last_unitid, 0)) {
link_pair->dev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0);
}
}
#endif
}
}
#endif
#if RAMINIT_SYSINFO == 0
@ -581,26 +584,26 @@ static int ht_setup_chain(device_t udev, unsigned upos)
{
unsigned offset_unitid = 0;
#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
offset_unitid = 1;
offset_unitid = 1;
#endif
/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
* On most boards this just happens. If a cpu has multiple
* non Coherent links the appropriate bus registers for the
* links needs to be programed to point at bus 0.
*/
/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
* On most boards this just happens. If a cpu has multiple
* non Coherent links the appropriate bus registers for the
* links needs to be programed to point at bus 0.
*/
/* Make certain the HT bus is not enumerated */
ht_collapse_previous_enumeration(0, 0);
/* Make certain the HT bus is not enumerated */
ht_collapse_previous_enumeration(0, 0);
#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
offset_unitid = 1;
offset_unitid = 1;
#endif
#if RAMINIT_SYSINFO == 1
ht_setup_chainx(udev, upos, 0, offset_unitid, sysinfo);
#else
return ht_setup_chainx(udev, upos, 0, offset_unitid);
return ht_setup_chainx(udev, upos, 0, offset_unitid);
#endif
}
static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt, uint8_t val)
@ -642,11 +645,11 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
unsigned devn = 1;
#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
if(i==0) // to check if it is sb ht chain
#endif
devn = HT_CHAIN_UNITID_BASE;
#endif
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
if(i==0) // to check if it is sb ht chain
#endif
devn = HT_CHAIN_UNITID_BASE;
#endif
reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
@ -672,59 +675,59 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)
{
uint32_t dword;
uint8_t link_type;
uint32_t dword;
uint8_t link_type;
unsigned regpos;
device_t dev;
/* This works on an Athlon64 because unimplemented links return 0 */
/* This works on an Athlon64 because unimplemented links return 0 */
regpos = 0x98 + (linkn * 0x20);
dev = PCI_DEV(0,0x18+node,0);
dword = pci_read_config32(dev, regpos);
link_type = dword & 0xff;
dword = pci_read_config32(dev, regpos);
link_type = dword & 0xff;
if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
regpos = 0x90 + (linkn * 0x20);
dword = pci_read_config32(dev, regpos );
dword = pci_read_config32(dev, regpos );
if (dword != val) {
pci_write_config32(dev, regpos, val);
return 1;
}
if (dword != val) {
pci_write_config32(dev, regpos, val);
return 1;
}
}
return 0;
return 0;
}
static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val)
{
int reset_needed;
uint8_t i;
int reset_needed;
uint8_t i;
reset_needed = 0;
reset_needed = 0;
for (i = 0; i < ht_c_num; i++) {
uint32_t reg;
uint8_t nodeid, linkn;
uint8_t busn;
unsigned devn;
for (i = 0; i < ht_c_num; i++) {
uint32_t reg;
uint8_t nodeid, linkn;
uint8_t busn;
unsigned devn;
reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
if((reg & 3) != 3) continue; // not enabled
reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
if((reg & 3) != 3) continue; // not enabled
nodeid = ((reg & 0xf0)>>4); // nodeid
linkn = ((reg & 0xf00)>>8); // link n
busn = (reg & 0xff0000)>>16; //busn
nodeid = ((reg & 0xf0)>>4); // nodeid
linkn = ((reg & 0xf00)>>8); // link n
busn = (reg & 0xff0000)>>16; //busn
for(devn = 0; devn < 0x20; devn++) {
reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1?
if ( (reg & 0xffff) == vendorid ) {
reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1?
if ( (reg & 0xffff) == vendorid ) {
reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
break;
}
}
}
}
}
return reset_needed;
return reset_needed;
}
@ -739,8 +742,8 @@ static int ht_setup_chains(uint8_t ht_c_num)
* non Coherent links the appropriate bus registers for the
* links needs to be programed to point at bus 0.
*/
uint8_t upos;
device_t udev;
uint8_t upos;
device_t udev;
uint8_t i;
#if RAMINIT_SYSINFO == 0
@ -775,14 +778,14 @@ static int ht_setup_chains(uint8_t ht_c_num)
#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
if(i==0) // to check if it is sb ht chain
#endif
offset_unitid = 1;
#endif
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
if(i==0) // to check if it is sb ht chain
#endif
offset_unitid = 1;
#endif
/* Make certain the HT bus is not enumerated */
ht_collapse_previous_enumeration(busn, offset_unitid);
/* Make certain the HT bus is not enumerated */
ht_collapse_previous_enumeration(busn, offset_unitid);
upos = ((reg & 0xf00)>>8) * 0x20 + 0x80;
udev = PCI_DEV(0, devpos, 0);
@ -794,10 +797,10 @@ static int ht_setup_chains(uint8_t ht_c_num)
#endif
#if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1)
/* You can use use this in romcc, because there is function call in romcc, recursive will kill you */
/* You can use use this in romcc, because there is function call in romcc, recursive will kill you */
bus = busn; // we need 32 bit
#if RAMINIT_SYSINFO == 1
scan_pci_bus(bus, sysinfo);
scan_pci_bus(bus, sysinfo);
#else
reset_needed |= (scan_pci_bus(bus)>>16); // take out reset_needed that stored in upword
#endif
@ -822,11 +825,11 @@ static void ht_setup_chains_x(struct sys_info *sysinfo)
static int ht_setup_chains_x(void)
#endif
{
uint8_t nodeid;
uint32_t reg;
uint8_t nodeid;
uint32_t reg;
uint32_t tempreg;
uint8_t next_busn;
uint8_t ht_c_num;
uint8_t next_busn;
uint8_t ht_c_num;
uint8_t nodes;
#if K8_ALLOCATE_IO_RANGE == 1
unsigned next_io_base;
@ -834,17 +837,17 @@ static int ht_setup_chains_x(void)
nodes = get_nodes();
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
/* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
/* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */
print_linkn_in("SBLink=", ((reg>>8) & 3) );
#if RAMINIT_SYSINFO == 1
sysinfo->sblk = (reg>>8) & 3;
sysinfo->sbbusn = 0;
sysinfo->nodes = nodes;
#endif
tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg);
tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg);
next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/
@ -858,95 +861,95 @@ static int ht_setup_chains_x(void)
#endif
/* clean others */
for(ht_c_num=1;ht_c_num<4; ht_c_num++) {
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
for(ht_c_num=1;ht_c_num<4; ht_c_num++) {
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
#if K8_ALLOCATE_IO_RANGE == 1
/* io range allocation */
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0);
#endif
}
}
for(nodeid=0; nodeid<nodes; nodeid++) {
device_t dev;
uint8_t linkn;
dev = PCI_DEV(0, 0x18+nodeid,0);
for(linkn = 0; linkn<3; linkn++) {
unsigned regpos;
regpos = 0x98 + 0x20 * linkn;
reg = pci_read_config32(dev, regpos);
if ((reg & 0x17) != 7) continue; /* it is not non conherent or not connected*/
for(nodeid=0; nodeid<nodes; nodeid++) {
device_t dev;
uint8_t linkn;
dev = PCI_DEV(0, 0x18+nodeid,0);
for(linkn = 0; linkn<3; linkn++) {
unsigned regpos;
regpos = 0x98 + 0x20 * linkn;
reg = pci_read_config32(dev, regpos);
if ((reg & 0x17) != 7) continue; /* it is not non conherent or not connected*/
print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf));
tempreg = 3 | (nodeid <<4) | (linkn<<8);
/*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */
for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
if(((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/
break;
}
}
if(ht_c_num == 4) break; /*used up only 4 non conherent allowed*/
/*update to 0xe0...*/
tempreg = 3 | (nodeid <<4) | (linkn<<8);
/*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */
for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
if(((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/
break;
}
}
if(ht_c_num == 4) break; /*used up only 4 non conherent allowed*/
/*update to 0xe0...*/
if((reg & 0xf) == 3) continue; /*SbLink so don't touch it */
print_linkn_in("\tbusn=", next_busn);
tempreg |= (next_busn<<16)|((next_busn+0x3f)<<24);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);
tempreg |= (next_busn<<16)|((next_busn+0x3f)<<24);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);
next_busn+=0x3f+1;
#if K8_ALLOCATE_IO_RANGE == 1
/* io range allocation */
tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);
tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ?
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg);
next_io_base += 0x3+0x1;
tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);
tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ?
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg);
next_io_base += 0x3+0x1;
#endif
}
}
/*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/
}
}
/*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/
for(nodeid = 1; nodeid<nodes; nodeid++) {
int i;
device_t dev;
dev = PCI_DEV(0, 0x18+nodeid,1);
for(i = 0; i< 4; i++) {
unsigned regpos;
regpos = 0xe0 + i * 4;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
pci_write_config32(dev, regpos, reg);
}
for(nodeid = 1; nodeid<nodes; nodeid++) {
int i;
device_t dev;
dev = PCI_DEV(0, 0x18+nodeid,1);
for(i = 0; i< 4; i++) {
unsigned regpos;
regpos = 0xe0 + i * 4;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
pci_write_config32(dev, regpos, reg);
}
#if K8_ALLOCATE_IO_RANGE == 1
/* io range allocation */
for(i = 0; i< 4; i++) {
unsigned regpos;
regpos = 0xc4 + i * 8;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
pci_write_config32(dev, regpos, reg);
}
for(i = 0; i< 4; i++) {
unsigned regpos;
regpos = 0xc0 + i * 8;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
pci_write_config32(dev, regpos, reg);
}
for(i = 0; i< 4; i++) {
unsigned regpos;
regpos = 0xc4 + i * 8;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
pci_write_config32(dev, regpos, reg);
}
for(i = 0; i< 4; i++) {
unsigned regpos;
regpos = 0xc0 + i * 8;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
pci_write_config32(dev, regpos, reg);
}
#endif
}
}
/* recount ht_c_num*/
uint8_t i=0;
for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
if(((reg & 0xf) != 0x0)) {
if(((reg & 0xf) != 0x0)) {
i++;
}
}
}
#if RAMINIT_SYSINFO == 1
sysinfo->ht_c_num = i;
ht_setup_chains(i, sysinfo);
ht_setup_chains(i, sysinfo);
sysinfo->sbdn = get_sbdn(sysinfo->sbbusn);
#else
return ht_setup_chains(i);

446
src/northbridge/amd/amdk8/northbridge.c
View File

@ -109,8 +109,8 @@ static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned lin
uint32_t busses, config_busses;
unsigned free_reg, config_reg;
unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain
unsigned max_bus;
unsigned min_bus;
unsigned max_bus;
unsigned min_bus;
unsigned max_devfn;
dev->link[link].cap = 0x80 + (link *0x20);
@ -158,29 +158,29 @@ static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned lin
* so we set the subordinate bus number to 0xff for the moment.
*/
#if SB_HT_CHAIN_ON_BUS0 > 0
// first chain will on bus 0
// first chain will on bus 0
if((nodeid == 0) && (sblink==link)) { // actually max is 0 here
min_bus = max;
}
min_bus = max;
}
#if SB_HT_CHAIN_ON_BUS0 > 1
// second chain will be on 0x40, third 0x80, forth 0xc0
else {
min_bus = ((max>>6) + 1) * 0x40;
}
max = min_bus;
#else
//other ...
else {
min_bus = ++max;
}
#endif
else {
min_bus = ((max>>6) + 1) * 0x40;
}
max = min_bus;
#else
//other ...
else {
min_bus = ++max;
}
#endif
#else
min_bus = ++max;
min_bus = ++max;
#endif
max_bus = 0xff;
max_bus = 0xff;
dev->link[link].secondary = min_bus;
dev->link[link].subordinate = max_bus;
dev->link[link].secondary = min_bus;
dev->link[link].subordinate = max_bus;
/* Read the existing primary/secondary/subordinate bus
* number configuration.
@ -251,38 +251,38 @@ static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned lin
static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
{
unsigned nodeid;
unsigned link;
unsigned sblink = 0;
unsigned nodeid;
unsigned link;
unsigned sblink = 0;
unsigned offset_unitid = 0;
nodeid = amdk8_nodeid(dev);
nodeid = amdk8_nodeid(dev);
if(nodeid==0) {
sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
if(nodeid==0) {
sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
#if SB_HT_CHAIN_ON_BUS0 > 0
#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
offset_unitid = 1;
#endif
offset_unitid = 1;
#endif
max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
#endif
}
}
for(link = 0; link < dev->links; link++) {
for(link = 0; link < dev->links; link++) {
#if SB_HT_CHAIN_ON_BUS0 > 0
if( (nodeid == 0) && (sblink == link) ) continue; //already done
#endif
offset_unitid = 0;
#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
if((nodeid == 0) && (sblink == link))
#endif
offset_unitid = 1;
#endif
max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid);
}
}
return max;
return max;
}
@ -473,8 +473,8 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
limit |= (nodeid & 7);
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n",
__func__, dev_path(dev), link);
printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n",
__func__, dev_path(dev), link);
base |= PCI_IO_BASE_VGA_EN;
}
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
@ -513,7 +513,7 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
* but it is too diffcult to deal with the resource allocation magic.
*/
#if CONFIG_CONSOLE_VGA_MULTI == 1
extern device_t vga_pri; // the primary vga device, defined in device.c
extern device_t vga_pri; // the primary vga device, defined in device.c
#endif
static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
@ -673,34 +673,34 @@ static void pci_domain_read_resources(device_t dev)
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
#else
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0);
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_IO, IORESOURCE_IO);
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0);
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_IO, IORESOURCE_IO);
/* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 1);
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM | IORESOURCE_PREFETCH);
/* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 1);
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM | IORESOURCE_PREFETCH);
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 2);
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM);
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 2);
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM);
#endif
}
@ -759,83 +759,83 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
struct hw_mem_hole_info mem_hole;
int i;
mem_hole.hole_startk = HW_MEM_HOLE_SIZEK;
mem_hole.hole_startk = HW_MEM_HOLE_SIZEK;
mem_hole.node_id = -1;
for (i = 0; i < 8; i++) {
uint32_t base;
uint32_t hole;
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
hole = pci_read_config32(__f1_dev[i], 0xf0);
if(hole & 1) { // we find the hole
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
mem_hole.node_id = i; // record the node No with hole
break; // only one hole
for (i = 0; i < 8; i++) {
uint32_t base;
uint32_t hole;
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
}
//We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
if(mem_hole.node_id==-1) {
uint32_t limitk_pri = 0;
for(i=0; i<8; i++) {
uint32_t base, limit;
unsigned base_k, limit_k;
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
hole = pci_read_config32(__f1_dev[i], 0xf0);
if(hole & 1) { // we find the hole
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
mem_hole.node_id = i; // record the node No with hole
break; // only one hole
}
}
base_k = (base & 0xffff0000) >> 2;
if(limitk_pri != base_k) { // we find the hole
mem_hole.hole_startk = limitk_pri;
mem_hole.node_id = i;
break; //only one hole
//We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
if(mem_hole.node_id==-1) {
uint32_t limitk_pri = 0;
for(i=0; i<8; i++) {
uint32_t base, limit;
unsigned base_k, limit_k;
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
limit = f1_read_config32(0x44 + (i << 3));
limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
limitk_pri = limit_k;
}
}
base_k = (base & 0xffff0000) >> 2;
if(limitk_pri != base_k) { // we find the hole
mem_hole.hole_startk = limitk_pri;
mem_hole.node_id = i;
break; //only one hole
}
limit = f1_read_config32(0x44 + (i << 3));
limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
limitk_pri = limit_k;
}
}
return mem_hole;
}
static void disable_hoist_memory(unsigned long hole_startk, int i)
{
int ii;
device_t dev;
uint32_t base, limit;
uint32_t hoist;
int ii;
device_t dev;
uint32_t base, limit;
uint32_t hoist;
uint32_t hole_sizek;
//1. find which node has hole
//2. change limit in that node.
//3. change base and limit in later node
//4. clear that node f0
//1. find which node has hole
//2. change limit in that node.
//3. change base and limit in later node
//4. clear that node f0
//if there is not mem hole enabled, we need to change it's base instead
hole_sizek = (4*1024*1024) - hole_startk;
for(ii=7;ii>i;ii--) {
for(ii=7;ii>i;ii--) {
base = f1_read_config32(0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
base = f1_read_config32(0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
limit = f1_read_config32(0x44 + (ii << 3));
f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
}
limit = f1_read_config32(0x44 + (i << 3));
f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
dev = __f1_dev[i];
f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
}
limit = f1_read_config32(0x44 + (i << 3));
f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
dev = __f1_dev[i];
hoist = pci_read_config32(dev, 0xf0);
if(hoist & 1) {
pci_write_config32(dev, 0xf0, 0);
@ -849,30 +849,30 @@ static void disable_hoist_memory(unsigned long hole_startk, int i)
static uint32_t hoist_memory(unsigned long hole_startk, int i)
{
int ii;
uint32_t carry_over;
device_t dev;
uint32_t base, limit;
uint32_t basek;
uint32_t hoist;
int ii;
uint32_t carry_over;
device_t dev;
uint32_t base, limit;
uint32_t basek;
uint32_t hoist;
carry_over = (4*1024*1024) - hole_startk;
carry_over = (4*1024*1024) - hole_startk;
for(ii=7;ii>i;ii--) {
for(ii=7;ii>i;ii--) {
base = f1_read_config32(0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
base = f1_read_config32(0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
limit = f1_read_config32(0x44 + (ii << 3));
f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
}
limit = f1_read_config32(0x44 + (i << 3));
f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
dev = __f1_dev[i];
base = pci_read_config32(dev, 0x40 + (i << 3));
basek = (base & 0xffff0000) >> 2;
f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
}
limit = f1_read_config32(0x44 + (i << 3));
f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
dev = __f1_dev[i];
base = pci_read_config32(dev, 0x40 + (i << 3));
basek = (base & 0xffff0000) >> 2;
if(basek == hole_startk) {
//don't need set memhole here, because hole off set will be 0, overflow
//so need to change base reg instead, new basek will be 4*1024*1024
@ -882,17 +882,17 @@ static uint32_t hoist_memory(unsigned long hole_startk, int i)
}
else
{
hoist = /* hole start address */
((hole_startk << 10) & 0xff000000) +
/* hole address to memory controller address */
(((basek + carry_over) >> 6) & 0x0000ff00) +
/* enable */
1;
hoist = /* hole start address */
((hole_startk << 10) & 0xff000000) +
/* hole address to memory controller address */
(((basek + carry_over) >> 6) & 0x0000ff00) +
/* enable */
1;
pci_write_config32(dev, 0xf0, hoist);
pci_write_config32(dev, 0xf0, hoist);
}
return carry_over;
return carry_over;
}
#endif
@ -911,68 +911,68 @@ static void pci_domain_set_resources(device_t dev)
#endif
#if 0
/* Place the IO devices somewhere safe */
io = find_resource(dev, 0);
io->base = DEVICE_IO_START;
/* Place the IO devices somewhere safe */
io = find_resource(dev, 0);
io->base = DEVICE_IO_START;
#endif
#if CONFIG_PCI_64BIT_PREF_MEM == 1
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
mem1 = find_resource(dev, 1);
mem2 = find_resource(dev, 2);
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
mem1 = find_resource(dev, 1);
mem2 = find_resource(dev, 2);
#if 1
printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
#endif
/* See if both resources have roughly the same limits */
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
{
/* If so place the one with the most stringent alignment first
*/
if (mem2->align > mem1->align) {
struct resource *tmp;
tmp = mem1;
mem1 = mem2;
mem2 = tmp;
}
/* Now place the memory as high up as it will go */
mem2->base = resource_max(mem2);
mem1->limit = mem2->base - 1;
mem1->base = resource_max(mem1);
}
else {
/* Place the resources as high up as they will go */
mem2->base = resource_max(mem2);
mem1->base = resource_max(mem1);
}
/* See if both resources have roughly the same limits */
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
{
/* If so place the one with the most stringent alignment first
*/
if (mem2->align > mem1->align) {
struct resource *tmp;
tmp = mem1;
mem1 = mem2;
mem2 = tmp;
}
/* Now place the memory as high up as it will go */
mem2->base = resource_max(mem2);
mem1->limit = mem2->base - 1;
mem1->base = resource_max(mem1);
}
else {
/* Place the resources as high up as they will go */
mem2->base = resource_max(mem2);
mem1->base = resource_max(mem1);
}
#if 1
printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
#endif
last = &dev->resource[dev->resources];
for(resource = &dev->resource[0]; resource < last; resource++)
{
last = &dev->resource[dev->resources];
for(resource = &dev->resource[0]; resource < last; resource++)
{
#if 1
resource->flags |= IORESOURCE_ASSIGNED;
resource->flags &= ~IORESOURCE_STORED;
resource->flags |= IORESOURCE_ASSIGNED;
resource->flags &= ~IORESOURCE_STORED;
#endif
compute_allocate_resource(&dev->link[0], resource,
BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
compute_allocate_resource(&dev->link[0], resource,
BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
resource->flags |= IORESOURCE_STORED;
report_resource_stored(dev, resource, "");
resource->flags |= IORESOURCE_STORED;
report_resource_stored(dev, resource, "");
}
}
#endif
@ -990,40 +990,40 @@ static void pci_domain_set_resources(device_t dev)
#endif
#if HW_MEM_HOLE_SIZEK != 0
/* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
* if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
* otherwise We reset the hole to the mmio_basek
*/
#if K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0()) {
#endif
/* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
* if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
* otherwise We reset the hole to the mmio_basek
*/
#if K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0()) {
#endif
mem_hole = get_hw_mem_hole_info();
if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore
mmio_basek = mem_hole.hole_startk;
if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore
mmio_basek = mem_hole.hole_startk;
reset_memhole = 0;
}
}
//mmio_basek = 3*1024*1024; // for debug to meet boundary
if(reset_memhole) {
if(mem_hole.node_id!=-1) { // We need to select HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....!
// We need to reset our Mem Hole, because We want more big HOLE than we already set
//Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead
disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
// We need to reset our Mem Hole, because We want more big HOLE than we already set
//Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead
disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
}
#if HW_MEM_HOLE_SIZE_AUTO_INC == 1
//We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
uint32_t basek_pri;
for (i = 0; i < 8; i++) {
uint32_t base;
for (i = 0; i < 8; i++) {
uint32_t base;
uint32_t basek;
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
basek = (base & 0xffff0000) >> 2;
if(mmio_basek == basek) {
@ -1033,7 +1033,7 @@ static void pci_domain_set_resources(device_t dev)
basek_pri = basek;
}
#endif
}
}
#if K8_REV_F_SUPPORT == 0
} // is_cpu_pre_e0
@ -1079,9 +1079,9 @@ static void pci_domain_set_resources(device_t dev)
#if HW_MEM_HOLE_SIZEK != 0
if(reset_memhole)
#if K8_REV_F_SUPPORT == 0
if(!is_cpu_pre_e0() )
if(!is_cpu_pre_e0() )
#endif
sizek += hoist_memory(mmio_basek,i);
sizek += hoist_memory(mmio_basek,i);
#endif
basek = mmio_basek;
@ -1237,15 +1237,15 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
// ----> you can mixed single core e0 and dual core e0 at any sequence
// That is the typical case
if(j == 0 ){
if(j == 0 ){
#if K8_REV_F_SUPPORT == 0
e0_later_single_core = is_e0_later_in_bsp(i); // single core
e0_later_single_core = is_e0_later_in_bsp(i); // single core
#else
e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
#endif
} else {
e0_later_single_core = 0;
}
} else {
e0_later_single_core = 0;
}
if(e0_later_single_core) {
printk_debug("\tFound Rev E or Rev F later single core\r\n");
@ -1273,7 +1273,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
jj = 0; // if create cpu core1 path in amd_siblings by core0
#endif
for (j = 0; j <=jj; j++ ) {
for (j = 0; j <=jj; j++ ) {
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;
@ -1301,14 +1301,14 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
if (cpu) {
cpu->path.u.apic.node_id = i;
cpu->path.u.apic.core_id = j;
if(sysconf.enabled_apic_ext_id) {
if(sysconf.lift_bsp_apicid) {
if(sysconf.enabled_apic_ext_id) {
if(sysconf.lift_bsp_apicid) {
cpu->path.u.apic.apic_id += sysconf.apicid_offset;
} else
{
if (cpu->path.u.apic.apic_id != 0)
cpu->path.u.apic.apic_id += sysconf.apicid_offset;
}
if (cpu->path.u.apic.apic_id != 0)
cpu->path.u.apic.apic_id += sysconf.apicid_offset;
}
}
printk_debug("CPU: %s %s\n",
dev_path(cpu), cpu->enabled?"enabled":"disabled");

306
src/northbridge/amd/amdk8/raminit.c
View File

@ -4,7 +4,7 @@
2005.02 yhlu add E0 memory hole support
*/
#if K8_REV_F_SUPPORT == 1
#include "raminit_f.c"
#include "raminit_f.c"
#else
#include <cpu/x86/mem.h>
@ -67,7 +67,7 @@ static void setup_resource_map(const unsigned int *register_values, int max)
static int controller_present(const struct mem_controller *ctrl)
{
return pci_read_config32(ctrl->f0, 0) == 0x11001022;
return pci_read_config32(ctrl->f0, 0) == 0x11001022;
}
#if RAMINIT_SYSINFO==1
@ -548,10 +548,10 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
int max;
#if 1
if (!controller_present(ctrl)) {
// print_debug("No memory controller present\r\n");
return;
}
if (!controller_present(ctrl)) {
// print_debug("No memory controller present\r\n");
return;
}
#endif
print_spew("setting up CPU");
print_spew_hex8(ctrl->node_id);
@ -563,8 +563,8 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
unsigned long reg;
#if 0
#if CONFIG_USE_PRINTK_IN_CAR
prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]);
#else
prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]);
#else
print_spew_hex32(register_values[i]);
print_spew(" <-");
print_spew_hex32(register_values[i+2]);
@ -810,9 +810,9 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz,
map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
map &= ~(0xf << (index * 4));
#if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) {
map &= ~(0xf << ( (index + 2) * 4));
}
if(sz.rank == 4) {
map &= ~(0xf << ( (index + 2) * 4));
}
#endif
@ -821,17 +821,17 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz,
if(is_cpu_pre_d0()) {
map |= (sz.side1 - (25 + 3)) << (index *4);
#if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) {
map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4);
}
if(sz.rank == 4) {
map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4);
}
#endif
}
else {
map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4);
#if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) {
map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4);
}
if(sz.rank == 4) {
map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4);
}
#endif
}
}
@ -913,11 +913,11 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk)
*/
if (tom_k >= 0x003f0000) {
#if HW_MEM_HOLE_SIZEK != 0
if(hole_startk != 0) {
tom_k = hole_startk;
} else
if(hole_startk != 0) {
tom_k = hole_startk;
} else
#endif
tom_k = 0x3f0000;
tom_k = 0x3f0000;
}
msr.lo = (tom_k & 0x003fffff) << 10;
msr.hi = (tom_k & 0xffc00000) >> 22;
@ -937,19 +937,19 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
/* 2GB */ (16 - 4),
};
static const uint8_t csbase_low_d0_shift[] = {
/* 32MB */ (13 - 4),
/* 64MB */ (14 - 4),
/* 128MB */ (14 - 4),
static const uint8_t csbase_low_d0_shift[] = {
/* 32MB */ (13 - 4),
/* 64MB */ (14 - 4),
/* 128MB */ (14 - 4),
/* 128MB */ (15 - 4),
/* 256MB */ (15 - 4),
/* 512MB */ (15 - 4),
/* 256MB */ (16 - 4),
/* 512MB */ (16 - 4),
/* 1GB */ (16 - 4),
/* 256MB */ (15 - 4),
/* 512MB */ (15 - 4),
/* 256MB */ (16 - 4),
/* 512MB */ (16 - 4),
/* 1GB */ (16 - 4),
/* 1GB */ (17 - 4),
/* 2GB */ (17 - 4),
};
/* 2GB */ (17 - 4),
};
/* cs_base_high is not changed */
@ -988,15 +988,15 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
}
value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
cs_mode =( value >> ((index>>1)*4)) & 0xf;
if(cs_mode == 0 ) continue;
if(common_cs_mode == 0) {
common_cs_mode = cs_mode;
}
/* The size differed fail */
if(common_cs_mode != cs_mode) {
return 0;
}
cs_mode =( value >> ((index>>1)*4)) & 0xf;
if(cs_mode == 0 ) continue;
if(common_cs_mode == 0) {
common_cs_mode = cs_mode;
}
/* The size differed fail */
if(common_cs_mode != cs_mode) {
return 0;
}
}
/* Chip selects can only be interleaved when there is
@ -1011,23 +1011,23 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
if(is_cpu_pre_d0()){
csbase_inc = 1 << csbase_low_shift[common_cs_mode];
if(is_dual_channel(ctrl)) {
/* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
// print_debug("8 4GB chip selects cannot be interleaved\r\n");
return 0;
}
/* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
// print_debug("8 4GB chip selects cannot be interleaved\r\n");
return 0;
}
csbase_inc <<=1;
}
}
else {
csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode];
if(is_dual_channel(ctrl)) {
if( (bits==3) && (common_cs_mode > 8)) {
// print_debug("8 cs_mode>8 chip selects cannot be interleaved\r\n");
return 0;
if( (bits==3) && (common_cs_mode > 8)) {
// print_debug("8 cs_mode>8 chip selects cannot be interleaved\r\n");
return 0;
}
csbase_inc <<=1;
}
}
}
/* Compute the initial values for csbase and csbask.
@ -1571,12 +1571,12 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
#if QRANK_DIMM_SUPPORT
if(dimm_mask == (3|(3<<DIMM_SOCKETS)) ) {
int ranks = 4;
for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
int val;
if (!(dimm_mask & (1 << i))) {
continue;
}
val = spd_read_byte(ctrl->channel0[i], 5);
if (!(dimm_mask & (1 << i))) {
continue;
}
val = spd_read_byte(ctrl->channel0[i], 5);
if(val!=ranks) {
ranks = val;
break;
@ -1844,7 +1844,7 @@ static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_pa
}
#if QRANK_DIMM_SUPPORT == 1
rank = spd_read_byte(ctrl->channel0[i], 5); /* number of physical banks */
rank = spd_read_byte(ctrl->channel0[i], 5); /* number of physical banks */
if (rank < 0) {
return -1;
}
@ -2154,108 +2154,108 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
#if HW_MEM_HOLE_SIZEK != 0
static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i)
{
int ii;
uint32_t carry_over;
device_t dev;
uint32_t base, limit;
uint32_t basek;
uint32_t hoist;
int j;
int ii;
uint32_t carry_over;
device_t dev;
uint32_t base, limit;
uint32_t basek;
uint32_t hoist;
int j;
carry_over = (4*1024*1024) - hole_startk;
carry_over = (4*1024*1024) - hole_startk;
for(ii=controllers - 1;ii>i;ii--) {
base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
for(ii=controllers - 1;ii>i;ii--) {
base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
for(j = 0; j < controllers; j++) {
pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
}
}
limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
for(j = 0; j < controllers; j++) {
pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
}
dev = ctrl[i].f1;
base = pci_read_config32(dev, 0x40 + (i << 3));
basek = (base & 0xffff0000) >> 2;
if(basek == hole_startk) {
//don't need set memhole here, because hole off set will be 0, overflow
//so need to change base reg instead, new basek will be 4*1024*1024
base &= 0x0000ffff;
base |= (4*1024*1024)<<2;
for(j = 0; j < controllers; j++) {
pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
}
}
for(j = 0; j < controllers; j++) {
pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
}
}
limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
for(j = 0; j < controllers; j++) {
pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
}
dev = ctrl[i].f1;
base = pci_read_config32(dev, 0x40 + (i << 3));
basek = (base & 0xffff0000) >> 2;
if(basek == hole_startk) {
//don't need set memhole here, because hole off set will be 0, overflow
//so need to change base reg instead, new basek will be 4*1024*1024
base &= 0x0000ffff;
base |= (4*1024*1024)<<2;
for(j = 0; j < controllers; j++) {
pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
}
}
else {
hoist = /* hole start address */
((hole_startk << 10) & 0xff000000) +
/* hole address to memory controller address */
(((basek + carry_over) >> 6) & 0x0000ff00) +
/* enable */
1;
pci_write_config32(dev, 0xf0, hoist);
hoist = /* hole start address */
((hole_startk << 10) & 0xff000000) +
/* hole address to memory controller address */
(((basek + carry_over) >> 6) & 0x0000ff00) +
/* enable */
1;
pci_write_config32(dev, 0xf0, hoist);
}
return carry_over;
return carry_over;
}
static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
{
uint32_t hole_startk;
int i;
uint32_t hole_startk;
int i;
hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK;
hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK;
#if HW_MEM_HOLE_SIZE_AUTO_INC == 1
/* We need to double check if hole_startk is valid.
* If it is equal to the dram base address in K (base_k),
* we need to decrease it.
*/
uint32_t basek_pri;
for(i=0; i<controllers; i++) {
uint32_t base;
unsigned base_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
base_k = (base & 0xffff0000) >> 2;
if(base_k == hole_startk) {
uint32_t basek_pri;
for(i=0; i<controllers; i++) {
uint32_t base;
unsigned base_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
base_k = (base & 0xffff0000) >> 2;
if(base_k == hole_startk) {
/* decrease memory hole startk to make sure it is
* in the middle of the previous node
*/
hole_startk -= (base_k - basek_pri)>>1;
break; /* only one hole */
}
basek_pri = base_k;
}
hole_startk -= (base_k - basek_pri)>>1;
break; /* only one hole */
}
basek_pri = base_k;
}
#endif
/* Find node number that needs the memory hole configured */
for(i=0; i<controllers; i++) {
uint32_t base, limit;
unsigned base_k, limit_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
base_k = (base & 0xffff0000) >> 2;
limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
/* Find node number that needs the memory hole configured */
for(i=0; i<controllers; i++) {
uint32_t base, limit;
unsigned base_k, limit_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
base_k = (base & 0xffff0000) >> 2;
limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
if ((base_k <= hole_startk) && (limit_k > hole_startk)) {
unsigned end_k;
hoist_memory(controllers, ctrl, hole_startk, i);
end_k = memory_end_k(ctrl, controllers);
set_top_mem(end_k, hole_startk);
break; /* only one hole */
}
}
unsigned end_k;
hoist_memory(controllers, ctrl, hole_startk, i);
end_k = memory_end_k(ctrl, controllers);
set_top_mem(end_k, hole_startk);
break; /* only one hole */
}
}
}
@ -2369,10 +2369,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
}
#if HW_MEM_HOLE_SIZEK != 0
// init hw mem hole here
/* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
// init hw mem hole here
/* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
if(!is_cpu_pre_e0())
set_hw_mem_hole(controllers, ctrl);
set_hw_mem_hole(controllers, ctrl);
#endif
//FIXME add enable node interleaving here -- yhlu
@ -2408,24 +2408,24 @@ static void set_sysinfo_in_ram(unsigned val)
static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr)
{
int i;
int j;
struct mem_controller *ctrl;
for(i=0;i<controllers; i++) {
ctrl = &ctrl_a[i];
ctrl->node_id = i;
ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
ctrl->f1 = PCI_DEV(0, 0x18+i, 1);
ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
int i;
int j;
struct mem_controller *ctrl;
for(i=0;i<controllers; i++) {
ctrl = &ctrl_a[i];
ctrl->node_id = i;
ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
ctrl->f1 = PCI_DEV(0, 0x18+i, 1);
ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
if(spd_addr == (void *)0) continue;
if(spd_addr == (void *)0) continue;
for(j=0;j<DIMM_SOCKETS;j++) {
ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];
}
}
for(j=0;j<DIMM_SOCKETS;j++) {
ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];
}
}
}
#endif

1228
src/northbridge/amd/amdk8/raminit_f_dqs.c
View File

File diff suppressed because it is too large Load Diff

18
src/northbridge/amd/amdk8/raminit_test.c
View File

@ -128,20 +128,20 @@ static void hlt(void)
unsigned long log2(unsigned long x)
{
// assume 8 bits per byte.
unsigned long i = 1 << (sizeof(x)*8 - 1);
unsigned long pow = sizeof(x) * 8 - 1;
// assume 8 bits per byte.
unsigned long i = 1 << (sizeof(x)*8 - 1);
unsigned long pow = sizeof(x) * 8 - 1;
if (! x) {
if (! x) {
static const char errmsg[] = " called with invalid parameter of 0\n";
write(STDERR_FILENO, __func__, sizeof(__func__) - 1);
write(STDERR_FILENO, errmsg, sizeof(errmsg) - 1);
hlt();
}
for(; i > x; i >>= 1, pow--)
;
hlt();
}
for(; i > x; i >>= 1, pow--)
;
return pow;
return pow;
}
typedef struct msr_struct

36
src/northbridge/amd/amdk8/reset_test.c
View File

@ -54,29 +54,29 @@ static void set_bios_reset(void)
static unsigned node_link_to_bus(unsigned node, unsigned link)
{
unsigned reg;
unsigned reg;
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
unsigned config_map;
config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
if ((config_map & 3) != 3) {
continue;
}
if ((((config_map >> 4) & 7) == node) &&
(((config_map >> 8) & 3) == link))
{
return (config_map >> 16) & 0xff;
}
}
return 0;
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
unsigned config_map;
config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
if ((config_map & 3) != 3) {
continue;
}
if ((((config_map >> 4) & 7) == node) &&
(((config_map >> 8) & 3) == link))
{
return (config_map >> 16) & 0xff;
}
}
return 0;
}
static unsigned get_sblk(void)
{
uint32_t reg;
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
return ((reg>>8) & 3) ;
uint32_t reg;
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
return ((reg>>8) & 3) ;
}
static unsigned get_sbbusn(unsigned sblk)

312
src/northbridge/amd/amdk8/setup_resource_map.c
View File

@ -2,38 +2,38 @@
static void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base)
{
int i;
int i;
// print_debug("setting up resource map offset....");
#if 0
print_debug("\r\n");
print_debug("\r\n");
#endif
for(i = 0; i < max; i += 3) {
device_t dev;
unsigned where;
unsigned long reg;
for(i = 0; i < max; i += 3) {
device_t dev;
unsigned where;
unsigned long reg;
#if 0
#if CONFIG_USE_PRINTK_IN_CAR
prink_debug("%08x <- %08x\r\n", register_values[i] + offset_pci_dev, register_values[i+2]);
#else
print_debug_hex32(register_values[i] + offset_pci_dev);
print_debug(" <-");
print_debug_hex32(register_values[i+2]);
print_debug("\r\n");
#endif
prink_debug("%08x <- %08x\r\n", register_values[i] + offset_pci_dev, register_values[i+2]);
#else
print_debug_hex32(register_values[i] + offset_pci_dev);
print_debug(" <-");
print_debug_hex32(register_values[i+2]);
print_debug("\r\n");
#endif
#endif
dev = (register_values[i] & ~0xfff) + offset_pci_dev;
where = register_values[i] & 0xfff;
reg = pci_read_config32(dev, where);
reg &= register_values[i+1];
reg |= register_values[i+2] + offset_io_base;
pci_write_config32(dev, where, reg);
dev = (register_values[i] & ~0xfff) + offset_pci_dev;
where = register_values[i] & 0xfff;
reg = pci_read_config32(dev, where);
reg &= register_values[i+1];
reg |= register_values[i+2] + offset_io_base;
pci_write_config32(dev, where, reg);
#if 0
reg = pci_read_config32(register_values[i]);
reg &= register_values[i+1];
reg |= register_values[i+2] & ~register_values[i+1];
pci_write_config32(register_values[i], reg);
reg = pci_read_config32(register_values[i]);
reg &= register_values[i+1];
reg |= register_values[i+2] & ~register_values[i+1];
pci_write_config32(register_values[i], reg);
#endif
}
}
// print_debug("done.\r\n");
}
@ -57,25 +57,25 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int
for(i = 0; i < max; i += 4) {
#if RES_DEBUG
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
i>>2, register_values[i],
register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
register_values[i+2],
register_values[i+3] + ( ( (register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0)
);
#else
print_debug_hex16(i>>2);
print_debug(": ");
print_debug_hex8(register_values[i]);
print_debug(" ");
print_debug_hex32(register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0) );
print_debug(" <- & ");
print_debug_hex32(register_values[i+2]);
print_debug(" | ");
print_debug_hex32(register_values[i+3] +
print_debug_hex16(i>>2);
print_debug(": ");
print_debug_hex8(register_values[i]);
print_debug(" ");
print_debug_hex32(register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0) );
print_debug(" <- & ");
print_debug_hex32(register_values[i+2]);
print_debug(" | ");
print_debug_hex32(register_values[i+3] +
(((register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0)
);
print_debug("\r\n");
print_debug("\r\n");
#endif
#endif
switch (register_values[i]) {
@ -139,194 +139,194 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int
}
static void setup_resource_map_x(const unsigned int *register_values, int max)
{
int i;
int i;
#if RES_DEBUG
print_debug("setting up resource map ex offset....");
print_debug("setting up resource map ex offset....");
#endif
#if RES_DEBUG
print_debug("\r\n");
print_debug("\r\n");
#endif
for(i = 0; i < max; i += 4) {
for(i = 0; i < max; i += 4) {
#if RES_DEBUG
#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
#else
print_debug_hex16(i/4);
print_debug(": ");
print_debug_hex8(register_values[i]);
print_debug(" ");
print_debug_hex32(register_values[i+1]);
print_debug(" <- & ");
print_debug_hex32(register_values[i+2]);
print_debug(" | ");
print_debug_hex32(register_values[i+3]);
print_debug("\r\n");
#endif
printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
#else
print_debug_hex16(i/4);
print_debug(": ");
print_debug_hex8(register_values[i]);
print_debug(" ");
print_debug_hex32(register_values[i+1]);
print_debug(" <- & ");
print_debug_hex32(register_values[i+2]);
print_debug(" | ");
print_debug_hex32(register_values[i+3]);
print_debug("\r\n");
#endif
#endif
switch (register_values[i]) {
case RES_PCI_IO: //PCI
{
device_t dev;
unsigned where;
unsigned long reg;
dev = register_values[i+1] & ~0xfff;
where = register_values[i+1] & 0xfff;
reg = pci_read_config32(dev, where);
reg &= register_values[i+2];
reg |= register_values[i+3];
pci_write_config32(dev, where, reg);
}
break;
case RES_PORT_IO_8: // io 8
{
unsigned where;
unsigned reg;
where = register_values[i+1];
reg = inb(where);
reg &= register_values[i+2];
reg |= register_values[i+3];
outb(reg, where);
}
break;
case RES_PORT_IO_32: //io32
{
unsigned where;
unsigned long reg;
where = register_values[i+1];
reg = inl(where);
reg &= register_values[i+2];
reg |= register_values[i+3];
outl(reg, where);
}
break;
switch (register_values[i]) {
case RES_PCI_IO: //PCI
{
device_t dev;
unsigned where;
unsigned long reg;
dev = register_values[i+1] & ~0xfff;
where = register_values[i+1] & 0xfff;
reg = pci_read_config32(dev, where);
reg &= register_values[i+2];
reg |= register_values[i+3];
pci_write_config32(dev, where, reg);
}
break;
case RES_PORT_IO_8: // io 8
{
unsigned where;
unsigned reg;
where = register_values[i+1];
reg = inb(where);
reg &= register_values[i+2];
reg |= register_values[i+3];
outb(reg, where);
}
break;
case RES_PORT_IO_32: //io32
{
unsigned where;
unsigned long reg;
where = register_values[i+1];
reg = inl(where);
reg &= register_values[i+2];
reg |= register_values[i+3];
outl(reg, where);
}
break;
#if 0
case RES_MEM_IO: //mem
{
unsigned where;
unsigned long reg;
where = register_values[i+1];
reg = read32(where);
reg &= register_values[i+2];
reg |= register_values[i+3];
write32( where, reg);
}
break;
case RES_MEM_IO: //mem
{
unsigned where;
unsigned long reg;
where = register_values[i+1];
reg = read32(where);
reg &= register_values[i+2];
reg |= register_values[i+3];
write32( where, reg);
}
break;
#endif
} // switch
} // switch
}
}
#if RES_DEBUG
print_debug("done.\r\n");
print_debug("done.\r\n");
#endif
}
static void setup_iob_resource_map(const unsigned int *register_values, int max)
{
int i;
int i;
for(i = 0; i < max; i += 3) {
unsigned where;
unsigned where;
unsigned reg;
where = register_values[i];
#if 0
udelay(2000);
print_debug_hex16(where);
udelay(2000);
print_debug_hex16(where);
#endif
reg = inb(where);
#if 0
print_debug("=");
print_debug_hex8(reg);
#endif
reg &= register_values[i+1];
reg |= register_values[i+2];
#if 0
print_debug(" <- ");
print_debug_hex8(reg);
#endif
outb(reg, where);
#if 0
print_debug(" -> ");
reg = inb(where);
print_debug_hex8(reg);
#if 0
print_debug("=");
print_debug_hex8(reg);
#endif
reg &= register_values[i+1];
reg |= register_values[i+2];
#if 0
print_debug(" <- ");
print_debug_hex8(reg);
#endif
outb(reg, where);
#if 0
print_debug(" -> ");
reg = inb(where);
print_debug_hex8(reg);
print_debug("\r\n");
#endif
}
}
}
static void setup_io_resource_map(const unsigned int *register_values, int max)
{
int i;
int i;
for(i = 0; i < max; i += 3) {
unsigned where;
unsigned where;
unsigned long reg;
where = register_values[i];
#if 0
udelay(2000);
print_debug_hex16(where);
udelay(2000);
print_debug_hex16(where);
#endif
reg = inl(where);
reg = inl(where);
#if 0
udelay(2000);
print_debug("=");
print_debug_hex32(reg);
print_debug("=");
print_debug_hex32(reg);
#endif
reg &= register_values[i+1];
reg |= register_values[i+2];
reg &= register_values[i+1];
reg |= register_values[i+2];
#if 0
udelay(2000);
print_debug(" <- ");
print_debug_hex32(reg);
print_debug(" <- ");
print_debug_hex32(reg);
#endif
outl(reg, where);
outl(reg, where);
#if 0
udelay(2000);
print_debug(" -> ");
reg = inl(where);
print_debug_hex32(reg);
print_debug(" -> ");
reg = inl(where);
print_debug_hex32(reg);
print_debug("\r\n");
#endif
}
}
}
#if 0
static void setup_mem_resource_map(const unsigned int *register_values, int max)
{
int i;
int i;
for(i = 0; i < max; i += 3) {
unsigned where;
unsigned where;
unsigned long reg;
#if 0
print_debug_hex32(register_values[i]);
print_debug(" <-");
print_debug_hex32(register_values[i+2]);
print_debug_hex32(register_values[i]);
print_debug(" <-");
print_debug_hex32(register_values[i+2]);
#endif
where = register_values[i];
reg = read32(where);
reg &= register_values[i+1];
reg |= register_values[i+2];
write32( where, reg);
where = register_values[i];
reg = read32(where);
reg &= register_values[i+1];
reg |= register_values[i+2];
write32( where, reg);
#if 0
print_debug(" RB ");
reg = read32(where);
print_debug_hex32(reg);
print_debug("\r\n");
print_debug(" RB ");
reg = read32(where);
print_debug_hex32(reg);
print_debug("\r\n");
#endif
}
}
}
#endif

108
src/northbridge/amd/amdk8/ssdt.dsl
View File

@ -10,45 +10,45 @@ DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-K8", "AMD-ACPI", 100925440)
Scope (\_SB.PCI0)
{
Name (BUSN, Package (0x04)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444
})
Name (MMIO, Package (0x10)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888,
0x99999999,
0xaaaaaaaa,
0xbbbbbbbb,
0xcccccccc,
0xdddddddd,
0xeeeeeeee,
0x11111111,
0x22222222
})
Name (PCIO, Package (0x08)
{
0x77777777,
0x88888888,
0x99999999,
0xaaaaaaaa,
0xbbbbbbbb,
0xcccccccc,
0xdddddddd,
0xeeeeeeee
})
Name (SBLK, 0x11)
Name (TOM1, 0xaaaaaaaa)
Name (BUSN, Package (0x04)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444
})
Name (MMIO, Package (0x10)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888,
0x99999999,
0xaaaaaaaa,
0xbbbbbbbb,
0xcccccccc,
0xdddddddd,
0xeeeeeeee,
0x11111111,
0x22222222
})
Name (PCIO, Package (0x08)
{
0x77777777,
0x88888888,
0x99999999,
0xaaaaaaaa,
0xbbbbbbbb,
0xcccccccc,
0xdddddddd,
0xeeeeeeee
})
Name (SBLK, 0x11)
Name (TOM1, 0xaaaaaaaa)
Name (SBDN, 0xbbbbbbbb)
Name (HCLK, Package (0x08)
{
@ -56,22 +56,22 @@ DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-K8", "AMD-ACPI", 100925440)
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888
0x55555555,
0x66666666,
0x77777777,
0x88888888
})
Name (HCDN, Package (0x08)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888
})
Name (HCDN, Package (0x08)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888
})
Name (CBST, 0x88)
}
}