mb/siemens/mc_ehl3: Add PTN3460 eDP-to-LVDS bridge

This board contains in addition to its base variant, mc_ehl2,
an LCD panel driven through the PTN3460 eDP-to-LVDS bridge.

This patch enables the PTN3460 support by adding the device to
devicetree.cb and board-specific configuration parameters in
lcd_panel.c, based upon a similar implementation in siemens/mc_apl7.

BUG=none
TEST=Boot with the LCD panel attached and observe whether
the picture is stable and free of artifacts coming from wrong
resolution, timing etc.

Change-Id: Ib8a1a6f47053406e42554c2dd33684165d54be08
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

src/mainboard/siemens/mc_ehl/variants/mc_ehl3/Kconfig

@@ -2,6 +2,7 @@ if BOARD_SIEMENS_MC_EHL3
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select DRIVERS_I2C_PTN3460
 	select DRIVERS_I2C_RV3028C7
 	select DRIVER_INTEL_I210
 	select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE

src/mainboard/siemens/mc_ehl/variants/mc_ehl3/Makefile.inc

@@ -3,4 +3,5 @@
 bootblock-y += gpio.c
 romstage-y += memory.c
 ramstage-y += gpio.c
+ramstage-y += lcd_panel.c
 ramstage-y += mainboard.c

src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb

@@ -163,7 +163,11 @@ chip soc/intel/elkhartlake
 			end
 		end
 		device pci 15.2 on	    # I2C2
-		# Add dummy I2C device to limit BUS speed to 100 kHz in OS
+			# Enable external display bridge (eDP to LVDS)
+			chip drivers/i2c/ptn3460
+				device i2c 0x20 on end  # PTN3460 DP2LVDS Bridge
+			end
+			# Add dummy I2C device to limit BUS speed to 100 kHz in OS
 			chip drivers/i2c/generic
 				register "hid" = ""PRP0001""
 				register "speed" = "I2C_SPEED_STANDARD"

src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c

@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <drivers/i2c/ptn3460/ptn3460.h>
+#include <hwilib.h>
+#include <types.h>
+
+/** \brief This function provides EDID data to the driver for DP2LVDS Bridge (PTN3460)
+ * @param  edid_data	pointer to EDID data in driver
+*/
+enum cb_err mb_get_edid(uint8_t edid_data[0x80])
+{
+	const char *hwi_block = "hwinfo.hex";
+
+	if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block);
+		return CB_ERR;
+	}
+
+	/* Get EDID data from hwinfo block */
+	if (hwilib_get_field(Edid, edid_data, PTN_EDID_LEN) != PTN_EDID_LEN) {
+		printk(BIOS_ERR, "LCD: No EDID data available in %s\n", hwi_block);
+		return CB_ERR;
+	}
+	return CB_SUCCESS;
+}
+
+/** \brief This function provides EDID block [0..6] to the driver for DP2LVDS Bridge (PTN3460)
+ * which has to be used.
+*/
+uint8_t mb_select_edid_table(void)
+{
+	return 6; /* With this mainboard we use EDID block 6 for emulation in PTN3460. */
+}
+
+/** \brief Function to enable mainboard to adjust the config data of PTN3460.
+ * @param   *cfg_ptr  Pointer to the PTN config structure to modify.
+ * @return  -1 on error; PTN_CFG_MODIFIED if data was modified and needs to be updated.
+*/
+int mb_adjust_cfg(struct ptn_3460_config *cfg)
+{
+	const char *hwi_block = "hwinfo.hex";
+	uint8_t disp_con = 0, color_depth = 0;
+
+	/* Get display-specific configuration from hwinfo. */
+	if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block);
+		return -1;
+	}
+	if (hwilib_get_field(PF_DisplCon, &disp_con, sizeof(disp_con)) != sizeof(disp_con)) {
+		printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block);
+		return -1;
+	}
+	if (hwilib_get_field(PF_Color_Depth, &color_depth,
+			     sizeof(color_depth)) != sizeof(color_depth)) {
+		printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block);
+		return -1;
+	}
+
+	/* Set up configuration data according to the hwinfo block we got. */
+	cfg->dp_interface_ctrl = 0x00;
+	/* Use odd-bus for clock distribution only. */
+	cfg->lvds_interface_ctrl1 = 0x01;
+	if (disp_con == PF_DISPLCON_LVDS_DUAL) {
+		/* Turn on dual LVDS lane and clock. */
+		cfg->lvds_interface_ctrl1 |= 0x0b;
+	}
+	if (color_depth == PF_COLOR_DEPTH_6BIT) {
+		/* Use 18 bits per pixel. */
+		cfg->lvds_interface_ctrl1 |= 0x20;
+	}
+
+	/* Set up remaining board-specific LVDS parameters: */
+	/* No clock spreading, 300 mV LVDS swing. */
+	cfg->lvds_interface_ctrl2 = 0x03;
+	/* No lane/channel swapping */
+	cfg->lvds_interface_ctrl3 = 0x00;
+	/* Enable VDD to LVDS active delay (16 ms). */
+	cfg->t2_delay = 0x01;
+	/* LVDS to backlight active delay: 200 ms. */
+	cfg->t3_timing = 0x04;
+	/* Minimum re-power delay: 500 ms */
+	cfg->t12_timing = 0x0a;
+	/* Backlight off to LVDS inactive delay: 200 ms. */
+	cfg->t4_timing = 0x04;
+	/* Enable LVDS to VDD inactive delay. */
+	cfg->t5_delay = 0x01;
+	/* Enable backlight control. */
+	cfg->backlight_ctrl = 0x00;
+
+	return PTN_CFG_MODIFIED;
+}