mb/google/volteer/variants/eldrid: Configure USB2 port for Type-C

1. USB2 ports 3 and 8 assigned to Type-C connector
2. USB2 port 3 keep USB2_PORT_SHORT setting and add .type_c flag

BUG=b:177481076
TEST=tested on eldrid

Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I42a39318a151bdf1f5aeb84bb1992be128cb4a4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Nick Chen 2021-01-14 14:23:21 +08:00 committed by Patrick Georgi
parent 37765930ec
commit d6375cf556
1 changed files with 12 additions and 1 deletions

View File

@ -66,7 +66,15 @@ chip soc/intel/tigerlake
register "usb2_ports[2]" = "USB2_PORT_EMPTY" register "usb2_ports[2]" = "USB2_PORT_EMPTY"
#improve the USB2 Port1 eye diagram #improve the USB2 Port1 eye diagram
register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" register "usb2_ports[3]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_39P35MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_39P35MV,
.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
.type_c = 1,
}"
#lower camera driving #lower camera driving
register "usb2_ports[4]" = "{ register "usb2_ports[4]" = "{
@ -77,6 +85,9 @@ chip soc/intel/tigerlake
.pre_emp_bit = 0, .pre_emp_bit = 0,
}" }"
#Type-A / Type-C C0
register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
device domain 0 on device domain 0 on
device ref dptf on device ref dptf on
# DPTF Policy for Eldrid board # DPTF Policy for Eldrid board