soc/intel/cmn/fast_spi: Add API to set SPI controller VCL

This patch creates a helper function to set SPI controller VCL bit as
recommended by Intel Flash Security Specification.

BUG=b:211954778
TEST=Able to build google/brya and verified that SPI flash controller
MMIO register 0xC4 bit 30 is set.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie9a12db1bab81779fd8e7db90221d08da3c65011
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Subrata Banik 2022-04-13 20:30:53 +05:30
parent d5e7c63a85
commit d643165c64
3 changed files with 28 additions and 0 deletions

View File

@ -170,6 +170,23 @@ void fast_spi_pr_dlock(void)
write32(spibar + SPIBAR_DLOCK, dlock);
}
/*
* Set FAST_SPIBAR + VSCC0 (0xC4) register VCL (bit 30).
*/
void fast_spi_vscc0_lock(void)
{
void *spibar = fast_spi_get_bar();
/*
* SPI Flash Programming Guide Section 5.5.2 describes Vendor Component Lock (VCL).
* It is recommended to set the VCL bit. VCL applies to both VSCC0 and VSCC1.
* Without this bit being set, it is possible to modify Host/GbE VSCC register(s),
* which might results in undesired host and integrated GbE Serial Flash
* functionality.
*/
setbits32(spibar + SPIBAR_SFDP0_VSCC0, SPIBAR_VSCC0_VCL);
}
/*
* Set FAST_SPIBAR Soft Reset Data Register value.
*/

View File

@ -131,6 +131,13 @@
(SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
/*
* Register Offset of BIOS Vendor Specific Component Capabilities (VSCC)
* for Component 0 Register
*/
#define SPIBAR_SFDP0_VSCC0 0xc4
#define SPIBAR_VSCC0_VCL (1 << 30)
/* Bit definitions for PTINX (0xcc) register */
#define SPIBAR_PTINX_COMP_0 (0 << 14)
#define SPIBAR_PTINX_COMP_1 (1 << 14)

View File

@ -42,6 +42,10 @@ void fast_spi_lock_bar(void);
* FAST_SPI Protected Range (PR) registers.
*/
void fast_spi_pr_dlock(void);
/*
* Set FAST_SPIBAR + VSCC0 (0xC4) register VCL (bit 30).
*/
void fast_spi_vscc0_lock(void);
/*
* Set FAST_SPIBAR Soft Reset Data Register value.
*/