soc/intel/cmn/fast_spi: Add API to set SPI controller VCL
This patch creates a helper function to set SPI controller VCL bit as recommended by Intel Flash Security Specification. BUG=b:211954778 TEST=Able to build google/brya and verified that SPI flash controller MMIO register 0xC4 bit 30 is set. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie9a12db1bab81779fd8e7db90221d08da3c65011 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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@ -170,6 +170,23 @@ void fast_spi_pr_dlock(void)
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write32(spibar + SPIBAR_DLOCK, dlock);
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}
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/*
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* Set FAST_SPIBAR + VSCC0 (0xC4) register VCL (bit 30).
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*/
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void fast_spi_vscc0_lock(void)
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{
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void *spibar = fast_spi_get_bar();
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/*
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* SPI Flash Programming Guide Section 5.5.2 describes Vendor Component Lock (VCL).
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* It is recommended to set the VCL bit. VCL applies to both VSCC0 and VSCC1.
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* Without this bit being set, it is possible to modify Host/GbE VSCC register(s),
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* which might results in undesired host and integrated GbE Serial Flash
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* functionality.
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*/
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setbits32(spibar + SPIBAR_SFDP0_VSCC0, SPIBAR_VSCC0_VCL);
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}
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/*
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* Set FAST_SPIBAR Soft Reset Data Register value.
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*/
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@ -131,6 +131,13 @@
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(SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
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#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
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/*
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* Register Offset of BIOS Vendor Specific Component Capabilities (VSCC)
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* for Component 0 Register
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*/
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#define SPIBAR_SFDP0_VSCC0 0xc4
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#define SPIBAR_VSCC0_VCL (1 << 30)
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/* Bit definitions for PTINX (0xcc) register */
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#define SPIBAR_PTINX_COMP_0 (0 << 14)
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#define SPIBAR_PTINX_COMP_1 (1 << 14)
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@ -42,6 +42,10 @@ void fast_spi_lock_bar(void);
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* FAST_SPI Protected Range (PR) registers.
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*/
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void fast_spi_pr_dlock(void);
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/*
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* Set FAST_SPIBAR + VSCC0 (0xC4) register VCL (bit 30).
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*/
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void fast_spi_vscc0_lock(void);
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/*
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* Set FAST_SPIBAR Soft Reset Data Register value.
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*/
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