intel/apollolake: Add support to enable google ChromeEC
ChromeEC is needed for EC controlled features to work properly. This patch adds neccessary support in soc/intel so that mainboard asl files can include the ChromeEC e.g. PNOT method and LPCB and also the nvs fields. BUG = 53096 TEST = This patch is needed by the mainboard specific ASL change to include src/ec/google/chromeec/acpi/ec.asl Change-Id: Icecc437df05cd3efb41579317a353fd22526e0c9 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/14967 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* These devices are created at runtime */
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External (\_PR.CP00, DeviceObj)
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External (\_PR.CP01, DeviceObj)
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External (\_PR.CP02, DeviceObj)
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External (\_PR.CP03, DeviceObj)
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External (\_PR.CP04, DeviceObj)
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External (\_PR.CP05, DeviceObj)
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External (\_PR.CP06, DeviceObj)
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External (\_PR.CP07, DeviceObj)
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/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
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Method (PNOT)
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{
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If (LGreaterEqual (\PCNT, 2)) {
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Notify (\_PR.CP00, 0x81) // _CST
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Notify (\_PR.CP01, 0x81) // _CST
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}
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If (LGreaterEqual (\PCNT, 4)) {
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Notify (\_PR.CP02, 0x81) // _CST
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Notify (\_PR.CP03, 0x81) // _CST
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}
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If (LGreaterEqual (\PCNT, 8)) {
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Notify (\_PR.CP04, 0x81) // _CST
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Notify (\_PR.CP05, 0x81) // _CST
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Notify (\_PR.CP06, 0x81) // _CST
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Notify (\_PR.CP07, 0x81) // _CST
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}
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}
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/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */
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Method (PPCN)
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{
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If (LGreaterEqual (\PCNT, 2)) {
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Notify (\_PR.CP00, 0x80) // _PPC
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Notify (\_PR.CP01, 0x80) // _PPC
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}
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If (LGreaterEqual (\PCNT, 4)) {
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Notify (\_PR.CP02, 0x80) // _PPC
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Notify (\_PR.CP03, 0x80) // _PPC
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}
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If (LGreaterEqual (\PCNT, 8)) {
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Notify (\_PR.CP04, 0x80) // _PPC
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Notify (\_PR.CP05, 0x80) // _PPC
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Notify (\_PR.CP06, 0x80) // _PPC
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Notify (\_PR.CP07, 0x80) // _PPC
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}
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}
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/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
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Method (TNOT)
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{
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If (LGreaterEqual (\PCNT, 2)) {
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Notify (\_PR.CP00, 0x82) // _TPC
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Notify (\_PR.CP01, 0x82) // _TPC
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}
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If (LGreaterEqual (\PCNT, 4)) {
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Notify (\_PR.CP02, 0x82) // _TPC
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Notify (\_PR.CP03, 0x82) // _TPC
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}
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If (LGreaterEqual (\PCNT, 8)) {
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Notify (\_PR.CP04, 0x82) // _TPC
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Notify (\_PR.CP05, 0x82) // _TPC
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Notify (\_PR.CP06, 0x82) // _TPC
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Notify (\_PR.CP07, 0x82) // _TPC
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}
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}
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/* Return a package containing enabled processor entries */
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Method (PPKG)
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{
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If (LGreaterEqual (\PCNT, 8)) {
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Return (Package()
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{
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\_PR.CP00,
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\_PR.CP01,
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\_PR.CP02,
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\_PR.CP03,
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\_PR.CP04,
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\_PR.CP05,
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\_PR.CP06,
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\_PR.CP07
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})
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} ElseIf (LGreaterEqual (\PCNT, 4)) {
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Return (Package ()
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{
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\_PR.CP00,
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\_PR.CP01,
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\_PR.CP02,
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\_PR.CP03
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})
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} ElseIf (LGreaterEqual (\PCNT, 2)) {
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Return (Package ()
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{
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\_PR.CP00,
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\_PR.CP01
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})
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} Else {
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Return (Package ()
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{
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\_PR.CP00
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})
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}
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}
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@ -26,8 +26,13 @@ External (NVSA)
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OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
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Field (GNVS, ByteAcc, NoLock, Preserve)
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{
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/* Nothing here yet, folks */
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/* Miscellaneous */
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Offset (0x00),
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PCNT, 8, // 0x01 - Processor Count
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PPCM, 8, // 0x02 - Max PPC State
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LIDS, 8, // 0x03 - LID State
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PWRS, 8, // 0x04 - AC Power State
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DPTE, 8, // 0x05 - Enable DPTF
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/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
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Offset (0x100),
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@ -0,0 +1,23 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Intel LPC Bus Device - 0:1f.0 */
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Device (LPCB)
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{
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Name (_ADR, 0x001f0000)
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}
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@ -27,3 +27,6 @@
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#include "gpio.asl"
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#include "xhci.asl"
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/* LPC */
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#include "lpc.asl"
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@ -28,7 +28,12 @@
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struct global_nvs_t {
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/* Miscellaneous */
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uint8_t unused[256];
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uint8_t pcnt; /* 0x01 - Processor Count */
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uint8_t ppcm; /* 0x02 - Max PPC State */
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uint8_t lids; /* 0x03 - LID State */
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uint8_t pwrs; /* 0x04 - AC Power State */
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uint8_t dpte; /* 0x05 - Enable DPTF */
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uint8_t unused[251];
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/* ChromeOS specific (0x100 - 0xfff) */
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chromeos_acpi_t chromeos;
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