mainboard/google/kahlee: Enable EC wake on GPIO24

The grunt EC uses GPIO24 (EC_PCH_WAKE_L) to signal wake-up events to the AP.
On Stoney, GPIO24 maps to GEVENT (GPE) 15.

The kahlee EC uses GPIO2 (EC_PCH_WAKE_L) to signal wake-up events to the AP.
On Stoney, GPIO2 maps to GEVENT (GPE) 8.

BUG=b:78461678
TEST=powerd_dbus_suspend, tap any key on keyboard wakes from S3.
TEST=sign in, EC: lidclose, EC: lidopen => system wakes from S3.

Change-Id: Ib1809740837e686992ff70b81933159a5dff7595
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Daniel Kurtz 2018-04-18 17:57:09 -06:00 committed by Martin Roth
parent 75ed7781cc
commit d648730fe8
4 changed files with 12 additions and 0 deletions

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@ -20,6 +20,7 @@
#include <soc/southbridge.h> #include <soc/southbridge.h>
#include <stdlib.h> #include <stdlib.h>
#include <boardid.h> #include <boardid.h>
#include <variant/gpio.h>
/* /*
* As a rule of thumb, GPIO pins used by coreboot should be initialized at * As a rule of thumb, GPIO pins used by coreboot should be initialized at
@ -498,6 +499,14 @@ static const struct sci_source gpe_table[] = {
.level = SMI_SCI_EDG, .level = SMI_SCI_EDG,
}, },
/* EC_PCH_WAKE_L */
{
.scimap = EC_WAKE_GPI,
.gpe = EC_WAKE_GPI,
.direction = SMI_SCI_LVL_LOW,
.level = SMI_SCI_EDG,
},
/* H1_PCH_INT_ODL */ /* H1_PCH_INT_ODL */
{ {
.scimap = 22, .scimap = 22,

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@ -58,6 +58,7 @@
/* Enable LID switch */ /* Enable LID switch */
#define EC_ENABLE_LID_SWITCH #define EC_ENABLE_LID_SWITCH
#define EC_ENABLE_WAKE_PIN EC_WAKE_GPI
/* Enable EC backed ALS device in ACPI */ /* Enable EC backed ALS device in ACPI */
#define EC_ENABLE_ALS_DEVICE #define EC_ENABLE_ALS_DEVICE

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@ -42,5 +42,6 @@
/* These define the GPE, not the GPIO. */ /* These define the GPE, not the GPIO. */
#define EC_SCI_GPI 3 /* AGPIO 22 -> GPE 3 */ #define EC_SCI_GPI 3 /* AGPIO 22 -> GPE 3 */
#define EC_SMI_GPI 10 /* AGPIO 6 -> GPE 10 */ #define EC_SMI_GPI 10 /* AGPIO 6 -> GPE 10 */
#define EC_WAKE_GPI 15 /* AGPIO 24 -> GPE 15 */
#endif /* __BASEBOARD_GPIO_H__ */ #endif /* __BASEBOARD_GPIO_H__ */

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@ -46,5 +46,6 @@
/* These define the GPE, not the GPIO. */ /* These define the GPE, not the GPIO. */
#define EC_SCI_GPI 3 /* AGPIO 22 -> GPE 3 */ #define EC_SCI_GPI 3 /* AGPIO 22 -> GPE 3 */
#define EC_SMI_GPI 10 /* AGPIO 6 -> GPE 10 */ #define EC_SMI_GPI 10 /* AGPIO 6 -> GPE 10 */
#define EC_WAKE_GPI 8 /* AGPIO 2 -> GPE 8 */
#endif /* __VARIANT_GPIO_H__ */ #endif /* __VARIANT_GPIO_H__ */