zero warnings days: unify mp tables. fix warnings.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/amd/dbm690t/mptable.c

@@ -41,7 +41,7 @@ extern u32 sbdn_sb600;
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "ATI     ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "DBM690T     ";
 	struct mp_config_table *mc;
 	int j;

src/mainboard/amd/mahogany/mptable.c

@@ -42,7 +42,7 @@ extern u32 sbdn_sb700;
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "AMD     ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "MAHOGANY    ";
 	struct mp_config_table *mc;
 	int j;

src/mainboard/amd/mahogany_fam10/mptable.c

@@ -42,7 +42,7 @@ extern u32 sbdn_sb700;
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "AMD     ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "MAHOGANY    ";
 	struct mp_config_table *mc;
 	int j;

src/mainboard/amd/pistachio/mptable.c

@@ -41,7 +41,7 @@ extern u32 sbdn_sb600;
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "ATI     ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "PISTACHIO   ";
 	struct mp_config_table *mc;
 	int j;

src/mainboard/amd/serengeti_cheetah/mptable.c

@@ -15,7 +15,7 @@
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "AMD     ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "SERENGETI   ";
         struct mp_config_table *mc;
 

src/mainboard/amd/serengeti_cheetah_fam10/mptable.c

@@ -34,7 +34,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "AMD     ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "SERENGETI	";
 	struct mp_config_table *mc;
 

src/mainboard/arima/hdama/mptable.c

@@ -110,7 +110,7 @@ static unsigned max_apicid(void)
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "LNXI    ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "HDAMA       ";
 	struct mp_config_table *mc;
 	unsigned char bus_num;

src/mainboard/asrock/939a785gmh/mptable.c

@@ -42,7 +42,7 @@ extern u32 sbdn_sb700;
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "AMD     ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "MAHOGANY    ";
 	struct mp_config_table *mc;
 	int j;

src/mainboard/asus/a8n_e/mptable.c

@@ -37,7 +37,7 @@ extern unsigned bus_type[256];
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "ASUS    ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "A8N-E      ";
 	struct mp_config_table *mc;
 	unsigned sbdn;

src/mainboard/asus/a8v-e_se/mptable.c

@@ -26,7 +26,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "LNXB    ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "A8V-E SE    ";
 	struct mp_config_table *mc;
 	int bus_isa = 42;

src/mainboard/broadcom/blast/mptable.c

@@ -24,7 +24,7 @@ extern  unsigned sbdn2;
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "BROADCOM";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "BLAST       ";
         struct mp_config_table *mc;
 

src/mainboard/dell/s1850/mptable.c

@@ -7,7 +7,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "DELL    ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "S2850       ";
 	struct mp_config_table *mc;
 	unsigned char bus_num;

src/mainboard/gigabyte/ga_2761gxdk/mptable.c

@@ -38,7 +38,7 @@ extern unsigned bus_type[256];
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "GIGABYTE";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "GA-2761GXDK ";
         struct mp_config_table *mc;
 	unsigned sbdn;

src/mainboard/gigabyte/m57sli/mptable.c

@@ -39,7 +39,7 @@ extern unsigned bus_type[256];
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "GIGABYTE";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "M57SLI      ";
         struct mp_config_table *mc;
 	unsigned sbdn;

src/mainboard/hp/dl145_g3/mptable.c

@@ -46,7 +46,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "HP      ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "TREX        ";
 	struct mp_config_table *mc;
 

src/mainboard/hp/dl145_g3/romstage.c

@@ -185,7 +185,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		DIMM5, DIMM7, 0, 0,
 	};
 
-	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE 
+		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
 	int needs_reset;
 	unsigned bsp_apicid = 0;
@@ -216,8 +217,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 //	setup_early_ipmi_serial();
 	pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-
-	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+	printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 
 #if CONFIG_MEM_TRAIN_SEQ == 1
 	set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@@ -243,7 +243,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	{
 		msr_t msr;
 		msr=rdmsr(0xc0010042);
-		print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+		printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo);
 	}
 	enable_fid_change();
 	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -252,7 +252,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	{
 		msr_t msr;
 		msr=rdmsr(0xc0010042);
-		print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+		printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo);
 	}
 #endif
 
@@ -261,7 +261,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	// fidvid change will issue one LDTSTOP and the HT change will be effective too
 	if (needs_reset) {
-		print_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 		soft_reset();
 	}
 
@@ -278,6 +278,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
 	post_cache_as_ram();
-
 }
 

src/mainboard/ibm/e325/mptable.c

@@ -7,7 +7,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "IBM     ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "E325        ";
 	struct mp_config_table *mc;
 
@@ -49,6 +49,7 @@ static void *smp_write_config_table(void *v)
 			bus_isa++;
 		} else {
 			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
+			bus_8111_0 = 1;
 			bus_8111_1 = 4;
 			bus_isa = 5;
 		}

src/mainboard/ibm/e326/mptable.c

@@ -7,7 +7,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "IBM     ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "E325        ";
 	struct mp_config_table *mc;
 
@@ -49,6 +49,7 @@ static void *smp_write_config_table(void *v)
 			bus_isa++;
 		} else {
 			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
+			bus_8111_0 = 1;
 			bus_8111_1 = 4;
 			bus_isa = 5;
 		}
@@ -57,7 +58,6 @@ static void *smp_write_config_table(void *v)
 		dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
 		if (dev) {
 			bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
 		} else {
 			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
 			bus_8131_1 = 2;

src/mainboard/intel/eagleheights/debug.c

@@ -210,7 +210,7 @@ static inline void dump_bar14(unsigned dev)
 	print_debug("\n");
 }
 
-static void dump_pci_devices(void)
+static inline void dump_pci_devices(void)
 {
 	device_t dev;
 	for(dev = PCI_DEV(0, 0, 0);

src/mainboard/intel/eagleheights/mptable.c

@@ -61,7 +61,7 @@
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "Intel   ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "EagleHeights";
         struct mp_config_table *mc;
 	unsigned char bus_num, bus_chipset, bus_isa, bus_pci;

src/mainboard/intel/jarrell/mptable.c

@@ -7,7 +7,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "LNXI    ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "SE7520JR20  ";
 	struct mp_config_table *mc;
 	unsigned char bus_num;
@@ -16,7 +16,7 @@ static void *smp_write_config_table(void *v)
 	unsigned char bus_pxhd_2;
 	unsigned char bus_pxhd_3 = 0;
 	unsigned char bus_pxhd_4 = 0;
-	unsigned char bus_pxhd_x;
+	unsigned char bus_pxhd_x = 0;
 	unsigned char bus_ich5r_1;
 	unsigned int bus_pxhd_id;
 
@@ -137,6 +137,7 @@ static void *smp_write_config_table(void *v)
 		else {
 			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
 		}
+
 		/* pxhd apic 5 */
 		if(bus_pxhd_3) { /* Active riser pxhd */
 			dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,1));
@@ -164,7 +165,6 @@ static void *smp_write_config_table(void *v)
 			}
 		}
 	}
-
 	
 	/* ISA backward compatibility interrupts  */
 	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
@@ -218,8 +218,8 @@ static void *smp_write_config_table(void *v)
 	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 		bus_isa, 0x00, MP_APIC_ALL, 0x01);
 
+	/* FIXME verify I have the irqs handled for all of the risers */
 
-#warning "FIXME verify I have the irqs handled for all of the risers"
 	/* 2:3.0 PCI Slot 1 */
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 		bus_pxhd_1, (3<<2)|0, 0x9, 0x0);

src/mainboard/intel/mtarvon/mptable.c

@@ -29,7 +29,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "Intel   ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "Mt. Arvon   ";
 	struct mp_config_table *mc;
 	u8 bus_isa = 7;

src/mainboard/intel/truxton/mptable.c

@@ -27,7 +27,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "Intel   ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "Truxton     ";
 	struct mp_config_table *mc;
 	u8 bus_num;

src/mainboard/intel/xe7501devkit/mptable.c

@@ -145,7 +145,7 @@ static void xe7501devkit_register_interrupts(struct mp_config_table *mc)
 static void *smp_write_config_table(void* v)
 {
 	static const char sig[4] = MPC_SIGNATURE;
-	static const char oem[8] = "INTEL   ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "XE7501DEVKIT";
 	struct mp_config_table *mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 	memset(mc, 0, sizeof(*mc));

src/mainboard/iwill/dk8_htx/mptable.c

@@ -15,7 +15,7 @@
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "IWILL   ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "DK8-HTX     ";
         struct mp_config_table *mc;
 

src/mainboard/iwill/dk8s2/mptable.c

@@ -7,7 +7,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "IWILL   ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "DK8X        ";
 	struct mp_config_table *mc;
 	unsigned char bus_num;

src/mainboard/iwill/dk8x/mptable.c

@@ -7,7 +7,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "IWILL   ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "DK8X        ";
 	struct mp_config_table *mc;
 	unsigned char bus_num;

src/mainboard/kontron/kt690/mptable.c

@@ -41,7 +41,7 @@ extern u32 sbdn_sb600;
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "KONTRON ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "KT690       ";
 	struct mp_config_table *mc;
 	int j;

src/mainboard/msi/ms7135/mptable.c

@@ -41,7 +41,7 @@ extern unsigned bus_type[256];
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "MSI     ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "MS7135      ";
 	struct mp_config_table *mc;
 	unsigned sbdn;

src/mainboard/msi/ms7260/mptable.c

@@ -36,7 +36,7 @@ extern unsigned bus_type[256];
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "MSI     ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "MS-7260     ";
 	struct mp_config_table *mc;
 	unsigned int sbdn;

src/mainboard/msi/ms9185/mptable.c

@@ -43,7 +43,7 @@
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "MSI     ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "MS9185      ";
         struct mp_config_table *mc;
 

src/mainboard/msi/ms9282/mptable.c

@@ -37,7 +37,7 @@
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "MSI    ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "MS9282      ";
         struct mp_config_table *mc;
 	struct mb_sysconf_t *m;

src/mainboard/msi/ms9652_fam10/mptable.c

@@ -34,7 +34,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "MSI     ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "K9ND MS-9652";
 	struct mp_config_table *mc;
 	struct mb_sysconf_t *m;

src/mainboard/newisys/khepri/mptable.c

@@ -7,7 +7,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "NEWISYS ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "KHEPRI      ";
 	struct mp_config_table *mc;
 	unsigned char bus_num;

src/mainboard/nvidia/l1_2pvv/mptable.c

@@ -34,7 +34,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "NVIDIA  ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "L1_2PVV     ";
 	struct mp_config_table *mc;
 	struct mb_sysconf_t *m;

src/mainboard/sunw/ultra40/mptable.c

@@ -36,7 +36,7 @@ extern  unsigned sbdnb;
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "SUNW    ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "ultra40     ";
         struct mp_config_table *mc;
 

src/mainboard/sunw/ultra40/romstage.c

@@ -41,10 +41,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
 
-static void memreset_setup(void)
-{
-}
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -53,16 +49,17 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
 
 #define SUPERIO_GPIO_IO_BASE 0x400
 
-static void sio_gpio_setup(void){
-
+#ifdef ENABLE_ONBOARD_SCSI
+static void sio_gpio_setup(void)
+{
         unsigned value;
 
         /*Enable onboard scsi*/
         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L 
         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
-
 }
+#endif
 
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
@@ -111,11 +108,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void sio_setup(void)
 {
-
         unsigned value;
         uint32_t dword;
         uint8_t byte;
-
         
         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
         
@@ -127,25 +122,22 @@ static void sio_setup(void)
         dword |= (1<<29)|(1<<0);
         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
         
-#if  1  
         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
                 
         value =  lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
         value &= 0xbf; 
         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
-#endif
-
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
+			// Node 0
 			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
 			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+			// Node 1
 			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
 			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
-#endif
 	};
 
         int needs_reset;
@@ -205,7 +197,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	enable_smbus();
 
-	memreset_setup();
 	sdram_initialize(nodes, ctrl);
 
 	post_cache_as_ram();

src/mainboard/supermicro/h8dme/mptable.c

@@ -38,7 +38,7 @@ extern unsigned char bus_pcix[3]; // under bus_mcp55_2
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "SUPERMIC";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "H8DMR       ";
         struct mp_config_table *mc;
 	unsigned sbdn;

src/mainboard/supermicro/h8dmr/mptable.c

@@ -38,7 +38,7 @@ extern unsigned char bus_pcix[3]; // under bus_mcp55_2
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "SUPERMIC";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "H8DMR       ";
         struct mp_config_table *mc;
 	unsigned sbdn;

src/mainboard/supermicro/h8dmr_fam10/mptable.c

@@ -34,7 +34,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "SUPERMIC";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "H8DMR       ";
 	struct mp_config_table *mc;
 	struct mb_sysconf_t *m;

src/mainboard/supermicro/h8qme_fam10/mptable.c

@@ -35,7 +35,7 @@ extern unsigned sbdn3;
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "SUPERMIC";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "H8QME       ";
 	struct mp_config_table *mc;
 	struct mb_sysconf_t *m;

src/mainboard/supermicro/x6dai_g/mptable.c

@@ -7,7 +7,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "LNXI    ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "X6DAI-G     ";
 	struct mp_config_table *mc;
 	unsigned char bus_num;

src/mainboard/supermicro/x6dhe_g/mptable.c

@@ -7,7 +7,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "LNXI    ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "X6DHE       ";
 	struct mp_config_table *mc;
 	unsigned char bus_num;
@@ -43,11 +43,9 @@ static void *smp_write_config_table(void *v)
 		dev = dev_find_slot(0, PCI_DEVFN(0x1c,0));
 		if (dev) {
 			bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-		}
-		else {
+		} else {
 			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n");
-
-			bus_esb6300_2 = 6;
+			bus_esb6300_1 = 6;
 		}
 		/* esb6300_1 */
 		dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
@@ -55,33 +53,25 @@ static void *smp_write_config_table(void *v)
 			bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 			bus_isa	   = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 			bus_isa++;
-		}
-		else {
+		} else {
 			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
-
-			bus_esb6300_1 = 7;
+			bus_esb6300_2 = 7;
 			bus_isa = 8;
 		}
 		/* pxhd-1 */
 		dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
 		if (dev) {
 			bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-		}
-		else {
+		} else {
 			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
-
 			bus_pxhd_1 = 2;
 		}
 		/* pxhd-2 */
 		dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
 		if (dev) {
 			bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-		}
-		else {
+		} else {
 			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
-
 			bus_pxhd_2 = 3;
 		}
 	}
@@ -106,8 +96,7 @@ static void *smp_write_config_table(void *v)
 			if (res) {
 				smp_write_ioapic(mc, 0x04, 0x20, res->base);
 			}
-		}
-		else {
+		} else {
 			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
 			printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
 		}
@@ -118,14 +107,12 @@ static void *smp_write_config_table(void *v)
 			if (res) {
 				smp_write_ioapic(mc, 0x05, 0x20, res->base);
 			}
-		}
-		else {
+		} else {
 			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
 			printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
 		}
 	}
 
-	
 	/* ISA backward compatibility interrupts  */
 	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 		bus_isa, 0x00, 0x02, 0x00);
@@ -182,7 +169,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 		bus_isa, 0x00, MP_APIC_ALL, 0x01);
 
-#warning "FIXME verify I have the irqs handled for all of the risers"
+	/* FIXME verify I have the irqs handled for all of the risers */
 
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);

src/mainboard/supermicro/x6dhe_g2/mptable.c

@@ -7,7 +7,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "LNXI    ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "X6DHE       ";
 	struct mp_config_table *mc;
 	unsigned char bus_num;
@@ -43,11 +43,9 @@ static void *smp_write_config_table(void *v)
 		dev = dev_find_slot(0, PCI_DEVFN(0x1c,0));
 		if (dev) {
 			bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-		}
-		else {
+		} else {
 			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n");
-
-			bus_esb6300_2 = 6;
+			bus_esb6300_1 = 6;
 		}
 		/* esb6300_1 */
 		dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
@@ -55,33 +53,25 @@ static void *smp_write_config_table(void *v)
 			bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 			bus_isa	   = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 			bus_isa++;
-		}
-		else {
+		} else {
 			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
-
-			bus_esb6300_1 = 7;
+			bus_esb6300_2 = 7;
 			bus_isa = 8;
 		}
 		/* pxhd-1 */
 		dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
 		if (dev) {
 			bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-		}
-		else {
+		} else {
 			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
-
 			bus_pxhd_1 = 2;
 		}
 		/* pxhd-2 */
 		dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
 		if (dev) {
 			bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-		}
-		else {
+		} else {
 			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
-
 			bus_pxhd_2 = 3;
 		}
 	}
@@ -106,8 +96,7 @@ static void *smp_write_config_table(void *v)
 			if (res) {
 				smp_write_ioapic(mc, 0x04, 0x20, res->base);
 			}
-		}
-		else {
+		} else {
 			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
 			printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
 		}
@@ -118,14 +107,12 @@ static void *smp_write_config_table(void *v)
 			if (res) {
 				smp_write_ioapic(mc, 0x05, 0x20, res->base);
 			}
-		}
-		else {
+		} else {
 			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
 			printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
 		}
 	}
 
-	
 	/* ISA backward compatibility interrupts  */
 	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 		bus_isa, 0x00, 0x02, 0x00);
@@ -182,7 +169,7 @@ static void *smp_write_config_table(void *v)
 	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 		bus_isa, 0x00, MP_APIC_ALL, 0x01);
 
-#warning "FIXME verify I have the irqs handled for all of the risers"
+	/* FIXME verify I have the irqs handled for all of the risers */
 
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);

src/mainboard/supermicro/x6dhr_ig/mptable.c

@@ -7,7 +7,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "LNXI    ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "X6DHR-iG    ";
 	struct mp_config_table *mc;
 	unsigned char bus_num;

src/mainboard/supermicro/x6dhr_ig2/mptable.c

@@ -7,7 +7,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "LNXI    ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "X6DHR-iG    ";
 	struct mp_config_table *mc;
 	unsigned char bus_num;

src/mainboard/technexion/tim5690/mptable.c

@@ -41,7 +41,7 @@ extern u32 sbdn_sb600;
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "ATI     ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "TIM5690     ";
 	struct mp_config_table *mc;
 	int j;

src/mainboard/technexion/tim8690/mptable.c

@@ -41,7 +41,7 @@ extern u32 sbdn_sb600;
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "ATI     ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "TIM8690     ";
 	struct mp_config_table *mc;
 	int j;

src/mainboard/tyan/s2735/mptable.c

@@ -7,7 +7,7 @@
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "TYAN    ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "S2735       ";
         struct mp_config_table *mc;
 

src/mainboard/tyan/s2850/mptable.c

@@ -46,7 +46,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link)
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "TYAN    ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "S2850       ";
         struct mp_config_table *mc;
 

src/mainboard/tyan/s2875/mptable.c

@@ -44,7 +44,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link)
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "TYAN    ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "S2875       ";
         struct mp_config_table *mc;
 

src/mainboard/tyan/s2880/mptable.c

@@ -46,7 +46,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link)
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "TYAN    ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "S2880       ";
         struct mp_config_table *mc;
 

src/mainboard/tyan/s2881/mptable.c

@@ -23,7 +23,7 @@ extern  unsigned sbdn3;
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "TYAN    ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "S2881       ";
         struct mp_config_table *mc;
 

src/mainboard/tyan/s2882/mptable.c

@@ -46,7 +46,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link)
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "TYAN    ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "S2882       ";
         struct mp_config_table *mc;
 

src/mainboard/tyan/s2885/mptable.c

@@ -27,7 +27,7 @@ extern  unsigned sbdn5;
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "TYAN    ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "S2885       ";
         struct mp_config_table *mc;
 

src/mainboard/tyan/s2891/mptable.c

@@ -27,7 +27,7 @@ extern  unsigned sbdn3;
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "TYAN    ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "S2891       ";
 	struct mp_config_table *mc;
 	unsigned sbdn;

src/mainboard/tyan/s2892/mptable.c

@@ -27,7 +27,7 @@ extern  unsigned sbdn3;
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "TYAN    ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "S2892       ";
 	struct mp_config_table *mc;
 	unsigned sbdn;

src/mainboard/tyan/s2895/mptable.c

@@ -35,7 +35,7 @@ extern  unsigned sbdnb;
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "TYAN    ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "S2895       ";
 	struct mp_config_table *mc;
 	unsigned sbdn;

src/mainboard/tyan/s2912/get_bus_conf.c

@@ -27,9 +27,7 @@
 #if CONFIG_LOGICAL_CPUS==1
 #include <cpu/amd/multicore.h>
 #endif
-
 #include <cpu/amd/amdk8_sysconf.h>
-
 #include <stdlib.h>
 #include "mb_sysconf.h"
 
@@ -37,8 +35,11 @@
 struct mb_sysconf_t mb_sysconf;
 
 unsigned pci1234x[] =
-{	//Here you only need to set value in pci1234 for HT-IO that could be installed or not
-	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+{	
+	// Here you only need to set value in pci1234 for HT-IO that could be
+	// installed or not.
+	// You may need to preset pci1234 for HTIO board, please refer to
+	// src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
 	0x0000ff0,
 	0x0000ff0,
 	0x0000ff0,
@@ -49,7 +50,9 @@ unsigned pci1234x[] =
 //	0x0000ff0
 };
 unsigned hcdnx[] =
-{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+{ 
+	// HT Chain device num, actually it is unit id base of every ht device
+	// in chain, assume every chain only have 4 ht device at most
 	0x20202020,
 	0x20202020,
 	0x20202020,
@@ -60,39 +63,10 @@ unsigned hcdnx[] =
 //	0x20202020,
 };
 
-
-
-
 static unsigned get_bus_conf_done = 0;
 
-static unsigned get_hcid(unsigned i)
-{
-	unsigned id = 0;
-
-	unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
-
-	unsigned devn = sysconf.hcdn[i] & 0xff;
-
-	device_t dev;
-
-	dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
-
-	switch (dev->device) {
-	case 0x0369: //IO55
-		id = 4;
-		break;
-	}
-
-	// we may need more way to find out hcid: subsystem id? GPIO read ?
-
-	// we need use id for 1. bus num, 2. mptable, 3. acpi table
-
-	return id;
-}
-
 void get_bus_conf(void)
 {
-
 	unsigned apicid_base;
 	struct mb_sysconf_t *m;
 
@@ -122,24 +96,22 @@ void get_bus_conf(void)
 
 	m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
 
-		/* MCP55 */
-		dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
-		if (dev) {
-			m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-		}
-		else {
-			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
-		}
+	/* MCP55 */
+	dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
+	if (dev) {
+		m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	} else {
+		printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
+	}
 
-		for(i=2; i<8;i++) {
-			dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
-			if (dev) {
-				m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-			}
-			else {
-				printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
-			}
+	for(i=2; i<8;i++) {
+		dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
+		if (dev) {
+			m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+		} else {
+			printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
 		}
+	}
 
 	for(i=0; i< sysconf.hc_possible_num; i++) {
 		if(!(sysconf.pci1234[i] & 0x1) ) continue;
@@ -160,5 +132,5 @@ void get_bus_conf(void)
 	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
 #endif
 	m->apicid_mcp55 = apicid_base+0;
-
 }
+

src/mainboard/tyan/s2912/mptable.c

@@ -34,7 +34,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "TYAN    ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "S2895       ";
 	struct mp_config_table *mc;
 	struct mb_sysconf_t *m;

src/mainboard/tyan/s2912_fam10/mptable.c

@@ -34,7 +34,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "TYAN    ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "S2895       ";
 	struct mp_config_table *mc;
 	struct mb_sysconf_t *m;

src/mainboard/tyan/s4880/mptable.c

@@ -44,7 +44,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link)
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "TYAN    ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "S4880       ";
         struct mp_config_table *mc;
 

src/mainboard/tyan/s4882/mptable.c

@@ -45,7 +45,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link)
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "TYAN    ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "S4882       ";
         struct mp_config_table *mc;
 

src/mainboard/via/epia-n/mptable.c

@@ -9,7 +9,7 @@
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "LNXI    ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "P4DPE       ";
         struct mp_config_table *mc;
 

src/mainboard/via/pc2500e/mptable.c

@@ -35,7 +35,7 @@
 static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
-	static const char oem[8] = "VIA     ";
+	static const char oem[8] = "COREBOOT";
 	static const char productid[12] = "PC2500      ";
 	struct mp_config_table *mc;
 

src/northbridge/amd/amdmct/mct/mct_d.c

@@ -476,7 +476,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
 	}
 }
 
-
+#ifdef UNUSED_CODE
 static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat,
 				struct DCTStatStruc *pDCTstatA)
 {
@@ -503,7 +503,7 @@ static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat,
 		}
 	}
 }
-
+#endif
 
 static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
 				struct DCTStatStruc *pDCTstatA)
@@ -3337,7 +3337,7 @@ static void SetCSTriState(struct MCTStatStruc *pMCTstat,
 }
 
 
-
+#ifdef UNUSED_CODE
 static void SetCKETriState(struct MCTStatStruc *pMCTstat,
 				struct DCTStatStruc *pDCTstat, u8 dct)
 {
@@ -3377,7 +3377,7 @@ static void SetCKETriState(struct MCTStatStruc *pMCTstat,
 
 	Set_NB32_index_wait(dev, index_reg, index, val);
 }
-
+#endif
 
 static void SetODTTriState(struct MCTStatStruc *pMCTstat,
 				struct DCTStatStruc *pDCTstat, u8 dct)
@@ -3856,7 +3856,7 @@ static void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat,
 	}
 }
 
-
+#ifdef UNUSED_CODE
 static void mct_SetupSync_D(struct MCTStatStruc *pMCTstat,
 					struct DCTStatStruc *pDCTstat)
 {
@@ -3878,6 +3878,7 @@ static void mct_SetupSync_D(struct MCTStatStruc *pMCTstat,
 		Set_NB32(dev, 0x78, val);
 	}
 }
+#endif
 
 static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) {
 

src/northbridge/amd/amdmct/mct/mct_d_gcc.h

@@ -161,7 +161,7 @@ static u32 read32_fs(u32 addr_lo)
 	return value;
 }
 
-
+#ifdef UNUSED_CODE
 static u8 read8_fs(u32 addr_lo)
 {
 	u8 byte;
@@ -173,7 +173,7 @@ static u8 read8_fs(u32 addr_lo)
 	);
 	return byte;
 }
-
+#endif
 
 static void FlushDQSTestPattern_L9(u32 addr_lo)
 {
@@ -369,6 +369,7 @@ static u32 stream_to_int(u8 const *p)
 }
 
 
+#ifdef UNUSED_CODE
 static void oemSet_NB32(u32 addr, u32 val, u8 *valid)
 {
 }
@@ -379,6 +380,7 @@ static u32 oemGet_NB32(u32 addr,  u8 *valid)
 	*valid = 0;
 	return 0xffffffff;
 }
+#endif
 
 
 static u8 oemNodePresent_D(u8 Node, u8 *ret)

src/northbridge/amd/amdmct/wrappers/mcti_d.c

@@ -233,10 +233,12 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
 	pDCTstat->PresetmaxFreq = 400;
 }
 
-
+#ifdef UNUSED_CODE
 static void mctAdjustAutoCycTmg(void)
 {
 }
+#endif
+
 
 static void mctAdjustAutoCycTmg_D(void)
 {
@@ -292,10 +294,11 @@ static void mctHookAfterECC(void)
 {
 }
 
-
+#ifdef UNUSED_CODE
 static void mctInitMemGPIOs_A(void)
 {
 }
+#endif
 
 
 static void mctInitMemGPIOs_A_D(void)
@@ -308,9 +311,12 @@ static void mctNodeIDDebugPort_D(void)
 }
 
 
+#ifdef UNUSED_CODE
 static void mctWarmReset(void)
 {
 }
+#endif
+
 
 static void mctWarmReset_D(void)
 {

src/northbridge/intel/i3100/raminit.h

@@ -30,4 +30,6 @@ struct mem_controller {
 	u16 channel1[DIMM_SOCKETS];
 };
 
+void sdram_initialize(int controllers, const struct mem_controller *ctrl);
+
 #endif

src/superio/ite/it8712f/it8712f.h

@@ -32,3 +32,10 @@
 #define IT8712F_MIDI 0x08 /* MIDI port */
 #define IT8712F_GAME 0x09 /* GAME port */
 #define IT8712F_IR   0x0a /* Consumer IR */
+
+#ifndef __ROMCC__
+void it8712f_kill_watchdog(void);
+void it8712f_enable_serial(device_t dev, unsigned iobase);
+void it8712f_24mhz_clkin(void)
+void it8712f_enable_3vsbsw(void)
+#endif

src/superio/ite/it8712f/it8712f_early_serial.c

@@ -66,7 +66,7 @@ static void it8712f_exit_conf(void)
 	it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
 }
 
-static void it8712f_24mhz_clkin(void)
+void it8712f_24mhz_clkin(void)
 {
 	it8712f_enter_conf();
 
@@ -76,7 +76,7 @@ static void it8712f_24mhz_clkin(void)
 	it8712f_exit_conf();
 }
 
-static void it8712f_enable_3vsbsw(void)
+void it8712f_enable_3vsbsw(void)
 {
 
 	/* We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2!
@@ -102,7 +102,7 @@ static void it8712f_kill_watchdog(void)
 }
 
 /* Enable the peripheral devices on the IT8712F Super I/O chip. */
-static void it8712f_enable_serial(device_t dev, unsigned iobase)
+void it8712f_enable_serial(device_t dev, unsigned iobase)
 {
 
 	/* (1) Enter the configuration state (MB PnP mode). */