coreboot arm: Define function for setting cntfrq register
Define functions for setting cntfrq register in arm and arm64 arch. This allows SoCs to set this register independently of the architecture being used. BUG=None BRANCH=None TEST=Compiles successfully for nyan and rush Original-Change-Id: I93240419b2c012eee29a408deff34a42af943a63 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205580 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 768463fef5d630dec915aa0b95e7724d4a6f74b6) armv8: GPL license armv8 lib BUG=None BRANCH=None TEST=Compiles successfully. Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250950 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I298c3e76cb52f0876bce3dd4f54d875f62e9310a Reviewed-on: http://review.coreboot.org/8468 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Furquan Shaikh
Marc Jones
parent
732b83ed36
commit
d653ae8960
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@ -60,6 +60,7 @@ bootblock-y += memset.S
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bootblock-y += memcpy.S
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bootblock-y += memmove.S
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bootblock-y += div0.c
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bootblock-y += clock.c
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$(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) $$(VERSTAGE_LIB)
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@printf " LINK $(subst $(obj)/,,$(@))\n"
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@ -91,6 +92,7 @@ romstage-y += eabi_compat.c
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romstage-y += memset.S
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romstage-y += memcpy.S
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romstage-y += memmove.S
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romstage-y += clock.c
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VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o
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@ -115,6 +117,7 @@ ramstage-y += tables.c
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ramstage-y += memset.S
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ramstage-y += memcpy.S
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ramstage-y += memmove.S
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ramstage-y += clock.c
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ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
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$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(src)/arch/arm/ramstage.ld $(obj)/ldoptions
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@ -0,0 +1,36 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <stdint.h>
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#include <arch/clock.h>
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void set_cntfrq(uint32_t freq)
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{
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__asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" :: "r"(freq));
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}
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@ -0,0 +1,25 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __ARM_CLOCK_H_
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#define __ARM_CLOCK_H_
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void set_cntfrq(uint32_t);
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#endif //__ARM_CLOCK_H_
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@ -20,7 +20,7 @@
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##
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################################################################################
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lib_access = pstate.c sysctrl.c cache.c tlb.c misc.c
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lib_access = pstate.c sysctrl.c cache.c tlb.c misc.c clock.c
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ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV8_64),y)
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bootblock-y += $(lib_access)
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@ -0,0 +1,32 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*
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* clock.c: Functions for accessing clock and timer related registers
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* Reference: ARM Architecture Reference Manual, ARMv8-A edition
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*/
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#include <stdint.h>
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#include <arch/clock.h>
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void set_cntfrq(uint32_t freq)
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{
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__asm__ __volatile__("msr cntfrq_el0, %0" :: "r"(freq));
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}
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@ -0,0 +1,25 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __ARM_CLOCK_H_
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#define __ARM_CLOCK_H_
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void set_cntfrq(uint32_t);
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#endif //__ARM_CLOCK_H_
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@ -20,6 +20,7 @@
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <stdlib.h>
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#include <arch/clock.h>
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#include "clk_rst.h"
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#include "flow.h"
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#include "maincpu.h"
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@ -181,7 +182,7 @@ void clock_init_arm_generic_timer(void)
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{
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uint32_t freq = clock_get_osc_khz() * 1000;
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// Set the cntfrq register.
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__asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" :: "r"(freq));
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set_cntfrq(freq);
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// Record the system timer frequency.
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write32(freq, &sysctr->cntfid0);
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@ -20,6 +20,7 @@
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <stdlib.h>
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#include <arch/clock.h>
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#include "clk_rst.h"
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#include "flow.h"
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#include "maincpu.h"
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@ -180,12 +181,12 @@ int clock_get_pll_input_khz(void)
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void clock_init_arm_generic_timer(void)
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{
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uint32_t freq = clock_get_osc_khz() * 1000;
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// Set the cntfrq register.
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__asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" :: "r"(freq));
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/* Set the cntfrq register. */
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set_cntfrq(freq);
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// Record the system timer frequency.
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/* Record the system timer frequency. */
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write32(freq, &sysctr->cntfid0);
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// Enable the system counter.
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/* Enable the system counter. */
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uint32_t cntcr = read32(&sysctr->cntcr);
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cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG;
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write32(cntcr, &sysctr->cntcr);
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@ -282,7 +283,7 @@ static void graphics_pll(void)
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* I don't want to find out in a few months
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* that it is needed.
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*/
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u32 scfg = (1<<28) | (1<<24) | (1<<22);
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u32 scfg = (1 << 28) | (1 << 24) | (1 << 22);
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writel(scfg, cfg);
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init_pll(&clk_rst->plldp_base, &clk_rst->plldp_misc,
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osc_table[osc].plldp, PLLDPD2_MISC_LOCK_ENABLE);
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@ -309,8 +310,9 @@ clock_display(u32 frequency)
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* iterate all possible values. Note Tegra 124 supports 11 bits for n,
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* but our pll_fields has only 10 bits for n.
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*
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* Note values undershoot or overshoot target output frequency may not
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* work if the values are not in "safe" range by panel specification.
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* Note, values that undershoot or overshoot the target output frequency
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* may not work if the values are not in "safe" range by panel
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* specification.
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*/
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struct pllpad_dividers plld = { 0 };
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u32 ref = clock_get_pll_input_khz() * 1000, m, n, p = 0;
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@ -366,11 +368,10 @@ clock_display(u32 frequency)
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else
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plld.cpcon = 12;
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if (best_diff) {
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if (best_diff)
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printk(BIOS_ERR, "%s: Failed to match output frequency %u, "
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"best difference is %u.\n", __func__, frequency,
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best_diff);
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}
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printk(BIOS_DEBUG, "%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n",
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__func__, (ref / plld.m * plld.n) >> plld.p, ref, plld.m, plld.n,
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@ -424,10 +425,10 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
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u32 misc1 = ((setup << PLLM_MISC1_SETUP_SHIFT) |
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(ph45 << PLLM_MISC1_PD_LSHIFT_PH45_SHIFT) |
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(ph90 << PLLM_MISC1_PD_LSHIFT_PH90_SHIFT) |
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(ph135 << PLLM_MISC1_PD_LSHIFT_PH135_SHIFT)),
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misc2 = ((kvco << PLLM_MISC2_KVCO_SHIFT) |
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(kcp << PLLM_MISC2_KCP_SHIFT)),
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base;
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(ph135 << PLLM_MISC1_PD_LSHIFT_PH135_SHIFT));
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u32 misc2 = ((kvco << PLLM_MISC2_KVCO_SHIFT) |
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(kcp << PLLM_MISC2_KCP_SHIFT));
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u32 base;
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if (same_freq)
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emc_source |= CLK_SOURCE_EMC_MC_EMC_SAME_FREQ;
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@ -455,9 +456,9 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
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/* stable_time is required, before we can start to check lock. */
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udelay(stable_time);
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while (!(readl(&clk_rst->pllm_base) & PLL_BASE_LOCK)) {
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while (!(readl(&clk_rst->pllm_base) & PLL_BASE_LOCK))
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udelay(1);
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}
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/*
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* After PLLM reports being locked, we have to delay 10us before
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* enabling PLLM_OUT.
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@ -484,7 +485,7 @@ void clock_cpu0_config_and_reset(void *entry)
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/* Set active CPU cluster to G */
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clrbits_le32(&flow->cluster_control, 1);
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// Set up cclk_brst and divider.
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/* Set up cclk_brst and divider. */
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write32((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) |
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(CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) |
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(CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) |
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@ -494,21 +495,21 @@ void clock_cpu0_config_and_reset(void *entry)
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write32(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB,
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&clk_rst->super_cclk_div);
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// Enable the clocks for CPUs 0-3.
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/* Enable the clocks for CPUs 0-3. */
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uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr);
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cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP |
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CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP;
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write32(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr);
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// Enable other CPU related clocks.
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/* Enable other CPU related clocks. */
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setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU);
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setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPUG);
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setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPULP);
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// Disable the reset on the non-CPU parts of the fast cluster.
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/* Disable the reset on the non-CPU parts of the fast cluster. */
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write32(CRC_RST_CPUG_CLR_NONCPU,
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&clk_rst->rst_cpug_cmplx_clr);
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// Disable the various resets on the CPUs.
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/* Disable the various resets on the CPUs. */
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write32(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 |
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CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 |
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CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 |
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@ -520,10 +521,10 @@ void clock_cpu0_config_and_reset(void *entry)
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CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
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&clk_rst->rst_cpug_cmplx_clr);
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// Disable the reset on the non-CPU parts of the slow cluster.
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/* Disable the reset on the non-CPU parts of the slow cluster. */
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write32(CRC_RST_CPULP_CLR_NONCPU,
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&clk_rst->rst_cpulp_cmplx_clr);
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// Disable the various resets on the LP CPU.
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/* Disable the various resets on the LP CPU. */
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write32(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 |
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CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 |
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CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG,
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@ -532,11 +533,10 @@ void clock_cpu0_config_and_reset(void *entry)
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void clock_halt_avp(void)
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{
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for (;;) {
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for (;;)
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write32(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ |
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FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT,
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&flow->halt_cop_events);
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}
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}
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void clock_init(void)
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@ -601,22 +601,34 @@ void clock_init(void)
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void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
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{
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if (l) writel(l, &clk_rst->clk_enb_l_set);
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if (h) writel(h, &clk_rst->clk_enb_h_set);
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if (u) writel(u, &clk_rst->clk_enb_u_set);
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if (v) writel(v, &clk_rst->clk_enb_v_set);
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if (w) writel(w, &clk_rst->clk_enb_w_set);
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if (x) writel(x, &clk_rst->clk_enb_x_set);
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if (l)
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writel(l, &clk_rst->clk_enb_l_set);
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if (h)
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writel(h, &clk_rst->clk_enb_h_set);
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if (u)
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writel(u, &clk_rst->clk_enb_u_set);
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if (v)
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writel(v, &clk_rst->clk_enb_v_set);
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if (w)
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writel(w, &clk_rst->clk_enb_w_set);
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if (x)
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writel(x, &clk_rst->clk_enb_x_set);
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/* Give clocks time to stabilize. */
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udelay(IO_STABILIZATION_DELAY);
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if (l) writel(l, &clk_rst->rst_dev_l_clr);
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if (h) writel(h, &clk_rst->rst_dev_h_clr);
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if (u) writel(u, &clk_rst->rst_dev_u_clr);
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if (v) writel(v, &clk_rst->rst_dev_v_clr);
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if (w) writel(w, &clk_rst->rst_dev_w_clr);
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if (x) writel(x, &clk_rst->rst_dev_x_clr);
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if (l)
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writel(l, &clk_rst->rst_dev_l_clr);
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if (h)
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writel(h, &clk_rst->rst_dev_h_clr);
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if (u)
|
||||
writel(u, &clk_rst->rst_dev_u_clr);
|
||||
if (v)
|
||||
writel(v, &clk_rst->rst_dev_v_clr);
|
||||
if (w)
|
||||
writel(w, &clk_rst->rst_dev_w_clr);
|
||||
if (x)
|
||||
writel(x, &clk_rst->rst_dev_x_clr);
|
||||
}
|
||||
|
||||
void clock_reset_l(u32 bit)
|
||||
|
|
|
|||
Loading…
Reference in New Issue