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soc/amd/*/root_complex: don't report root complex IOAPIC resource twice 

Since the per PCI root IOAPIC is now reported as domain MMIO resource
and the IVRS code now again probes for the IOAPIC resource on the domain
device, the IOAPIC resource doesn't need to be reported as resource of
the northbridge PCI device any more.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8604bd321ec4239076b1be99dca095e47f8b75a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76600
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Felix Held 2023-07-18 23:33:40 +02:00
parent b8b0c66cff
commit d6656bed83
5 changed files with 0 additions and 15 deletions
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3
src/soc/amd/cezanne/root_complex.c
View File

@ -143,9 +143,6 @@ static void read_resources(struct device *dev)
mmconf_resource(dev, idx++);
/* GNB IOAPIC resource */
mmio_range(dev, IOMMU_IOAPIC_IDX, GNB_IO_APIC_ADDR, 0x1000);
/* Reserve fixed IOMMU MMIO region */
mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);

3
src/soc/amd/glinda/root_complex.c
View File

@ -158,9 +158,6 @@ static void read_resources(struct device *dev)
mmconf_resource(dev, idx++);
/* GNB IOAPIC resource */
mmio_range(dev, IOMMU_IOAPIC_IDX, GNB_IO_APIC_ADDR, 0x1000);
/* Reserve fixed IOMMU MMIO region */
mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);

3
src/soc/amd/mendocino/root_complex.c
View File

@ -186,9 +186,6 @@ static void read_resources(struct device *dev)
mmconf_resource(dev, idx++);
/* GNB IOAPIC resource */
mmio_range(dev, IOMMU_IOAPIC_IDX, GNB_IO_APIC_ADDR, 0x1000);
/* Reserve fixed IOMMU MMIO region */
mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);

3
src/soc/amd/phoenix/root_complex.c
View File

@ -158,9 +158,6 @@ static void read_resources(struct device *dev)
mmconf_resource(dev, idx++);
/* GNB IOAPIC resource */
mmio_range(dev, IOMMU_IOAPIC_IDX, GNB_IO_APIC_ADDR, 0x1000);
/* Reserve fixed IOMMU MMIO region */
mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);

3
src/soc/amd/picasso/root_complex.c
View File

@ -141,9 +141,6 @@ static void read_resources(struct device *dev)
mmconf_resource(dev, idx++);
/* GNB IOAPIC resource */
mmio_range(dev, IOMMU_IOAPIC_IDX, GNB_IO_APIC_ADDR, 0x1000);
/* Reserve fixed IOMMU MMIO region */
mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);