soc/intel/common: Bring DISPLAY_MTRRS into the light
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the "Debug" menu. It turned out, though, that the code looks rather generic. No need to hide it in soc/intel/. To not bloat src/Kconfig up any further, start a new `Kconfig.debug` hierarchy just for debug options. If somebody wants to review the code if it's 100% generic, we could even get rid of HAVE_DISPLAY_MTRRS. Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29684 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber
Patrick Georgi
parent
3032d76778
commit
d67edcae6e
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@ -79,8 +79,6 @@
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<tr bgcolor=#ffc0c0><td>Required</td><td>smm_region_size</td></tr>
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<tr bgcolor=#c0ffc0><td>Required</td><td>soc_after_ram_init</td></tr>
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<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_memory_init_params</td></tr>
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<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_mtrrs</td></tr>
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<tr bgcolor=#c0ffc0><td>Required</td><td>soc_get_variable_mtrr_count</td></tr>
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<tr bgcolor=#c0ffc0><td>Required</td><td>soc_memory_init_params</td></tr>
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<tr bgcolor=#ffffc0><td>Optional</td><td>soc_pre_ram_init</td></tr>
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<tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr>
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@ -234,8 +234,6 @@ Use the following steps to locate the FSP binary:
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc">src/drivers/intel/fsp1_1/cache_as_ram.inc</a>
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</li>
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<li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common
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specifically building
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/common/util.c">util.c</a>
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</li>
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</ol>
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</li>
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@ -670,6 +670,11 @@ source "payloads/Kconfig"
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menu "Debugging"
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comment "CPU Debug Settings"
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source "src/cpu/*/Kconfig.debug"
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comment "General Debug Settings"
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# TODO: Better help text and detailed instructions.
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config GDB_STUB
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bool "GDB debugging support"
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@ -16,9 +16,9 @@
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#include <arch/cpu.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <cpu/x86/mtrr.h>
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#include <main_decl.h>
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#include <program_loading.h>
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#include <soc/intel/common/util.h>
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/*
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* Systems without a native coreboot cache-as-ram teardown may implement
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@ -35,9 +35,7 @@ void main(void)
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/* Recover cbmem so infrastruture using it is functional. */
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cbmem_initialize();
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/* Display the MTRRs */
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if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
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soc_display_mtrrs();
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display_mtrrs();
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/* Load and run ramstage. */
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run_ramstage();
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@ -0,0 +1,6 @@
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config HAVE_DISPLAY_MTRRS
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bool
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config DISPLAY_MTRRS
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bool "Display intermediate MTRR settings"
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depends on HAVE_DISPLAY_MTRRS
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@ -1,3 +1,9 @@
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ramstage-y += mtrr.c
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romstage-y += earlymtrr.c
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bootblock-y += earlymtrr.c
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ramstage-y += mtrr.c
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romstage-y += earlymtrr.c
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bootblock-y += earlymtrr.c
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bootblock-y += debug.c
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romstage-y += debug.c
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postcar-y += debug.c
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ramstage-y += debug.c
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@ -16,23 +16,9 @@
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#include <console/console.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/mtrr.h>
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#include <soc/intel/common/util.h>
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#include <stddef.h>
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#include <stdint.h>
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uint32_t soc_get_variable_mtrr_count(uint64_t *msr)
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{
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union {
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uint64_t u64;
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msr_t s;
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} mtrrcap;
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mtrrcap.s = rdmsr(MTRR_CAP_MSR);
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if (msr != NULL)
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*msr = mtrrcap.u64;
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return mtrrcap.u64 & MTRR_CAP_VCNT;
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}
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static const char *soc_display_mtrr_type(uint32_t type)
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static const char *display_mtrr_type(uint32_t type)
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{
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switch (type) {
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default: return "reserved";
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@ -45,7 +31,7 @@ static const char *soc_display_mtrr_type(uint32_t type)
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}
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}
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static void soc_display_mtrr_fixed_types(uint64_t msr,
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static void display_mtrr_fixed_types(uint64_t msr,
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uint32_t starting_address, uint32_t memory_size)
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{
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uint32_t base_address;
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@ -64,7 +50,7 @@ static void soc_display_mtrr_fixed_types(uint64_t msr,
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if (next_type != type) {
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printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n",
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base_address, next_address - 1,
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soc_display_mtrr_type(type));
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display_mtrr_type(type));
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base_address = next_address;
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type = next_type;
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}
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@ -72,10 +58,10 @@ static void soc_display_mtrr_fixed_types(uint64_t msr,
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if (base_address != next_address)
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printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n",
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base_address, next_address - 1,
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soc_display_mtrr_type(type));
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display_mtrr_type(type));
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}
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static void soc_display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address,
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static void display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address,
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const char *name)
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{
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union {
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@ -85,10 +71,10 @@ static void soc_display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address,
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msr.s = rdmsr(msr_reg);
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printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name);
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soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x1000);
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display_mtrr_fixed_types(msr.u64, starting_address, 0x1000);
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}
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static void soc_display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address,
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static void display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address,
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const char *name)
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{
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union {
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@ -98,10 +84,10 @@ static void soc_display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address,
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msr.s = rdmsr(msr_reg);
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printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name);
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soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x4000);
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display_mtrr_fixed_types(msr.u64, starting_address, 0x4000);
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}
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static void soc_display_64k_mtrr(void)
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static void display_64k_mtrr(void)
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{
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union {
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uint64_t u64;
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@ -110,26 +96,24 @@ static void soc_display_64k_mtrr(void)
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msr.s = rdmsr(MTRR_FIX_64K_00000);
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printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_FIX64K_00000\n", msr.u64);
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soc_display_mtrr_fixed_types(msr.u64, 0, 0x10000);
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display_mtrr_fixed_types(msr.u64, 0, 0x10000);
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}
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static uint32_t soc_display_mtrrcap(void)
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static void display_mtrrcap(void)
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{
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uint64_t msr;
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uint32_t variable_mtrrs;
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msr_t msr;
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variable_mtrrs = soc_get_variable_mtrr_count(&msr);
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msr = rdmsr(MTRR_CAP_MSR);
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printk(BIOS_DEBUG,
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"0x%016llx: IA32_MTRRCAP: %s%s%s%d variable MTRRs\n",
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msr,
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(msr & MTRR_CAP_SMRR) ? "SMRR, " : "",
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(msr & MTRR_CAP_WC) ? "WC, " : "",
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(msr & MTRR_CAP_FIX) ? "FIX, " : "",
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variable_mtrrs);
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return variable_mtrrs;
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"0x%08x%08x: IA32_MTRRCAP: %s%s%s%u variable MTRRs\n",
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msr.hi, msr.lo,
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(msr.lo & MTRR_CAP_SMRR) ? "SMRR, " : "",
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(msr.lo & MTRR_CAP_WC) ? "WC, " : "",
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(msr.lo & MTRR_CAP_FIX) ? "FIX, " : "",
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msr.lo & MTRR_CAP_VCNT);
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}
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static void soc_display_mtrr_def_type(void)
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static void display_mtrr_def_type(void)
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{
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union {
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uint64_t u64;
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@ -141,13 +125,13 @@ static void soc_display_mtrr_def_type(void)
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msr.u64,
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(msr.u64 & MTRR_DEF_TYPE_EN) ? " E," : "",
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(msr.u64 & MTRR_DEF_TYPE_FIX_EN) ? " FE," : "",
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soc_display_mtrr_type((uint32_t)(msr.u64 &
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display_mtrr_type((uint32_t)(msr.u64 &
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MTRR_DEF_TYPE_MASK)));
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}
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static void soc_display_variable_mtrr(uint32_t msr_reg, int index,
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uint64_t address_mask)
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static void display_variable_mtrr(int index, uint64_t address_mask)
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{
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const uint32_t msr_reg = MTRR_PHYS_BASE(index);
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uint64_t base_address;
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uint64_t length;
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uint64_t mask;
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@ -168,7 +152,7 @@ static void soc_display_variable_mtrr(uint32_t msr_reg, int index,
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printk(BIOS_DEBUG,
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"0x%016llx: PHYBASE%d: Address = 0x%016llx, %s\n",
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msr_a.u64, index, base_address,
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soc_display_mtrr_type(msr_a.u64 & MTRR_DEF_TYPE_MASK));
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display_mtrr_type(msr_a.u64 & MTRR_DEF_TYPE_MASK));
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mask = (msr_m.u64 & 0xfffffffffffff000ULL) & address_mask;
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length = (~mask & address_mask) + 1;
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printk(BIOS_DEBUG,
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}
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}
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asmlinkage void soc_display_mtrrs(void)
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static void _display_mtrrs(void)
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{
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if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) {
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uint32_t address_bits;
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uint64_t address_mask;
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int i;
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int variable_mtrrs;
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uint32_t address_bits;
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uint64_t address_mask;
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int i;
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int variable_mtrrs;
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/* Display the fixed MTRRs */
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variable_mtrrs = soc_display_mtrrcap();
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soc_display_mtrr_def_type();
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soc_display_64k_mtrr();
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soc_display_16k_mtrr(MTRR_FIX_16K_80000, 0x80000,
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"IA32_MTRR_FIX16K_80000");
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soc_display_16k_mtrr(MTRR_FIX_16K_A0000, 0xa0000,
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"IA32_MTRR_FIX16K_A0000");
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soc_display_4k_mtrr(MTRR_FIX_4K_C0000, 0xc0000,
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"IA32_MTRR_FIX4K_C0000");
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soc_display_4k_mtrr(MTRR_FIX_4K_C8000, 0xc8000,
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"IA32_MTRR_FIX4K_C8000");
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soc_display_4k_mtrr(MTRR_FIX_4K_D0000, 0xd0000,
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"IA32_MTRR_FIX4K_D0000");
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soc_display_4k_mtrr(MTRR_FIX_4K_D8000, 0xd8000,
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"IA32_MTRR_FIX4K_D8000");
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soc_display_4k_mtrr(MTRR_FIX_4K_E0000, 0xe0000,
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"IA32_MTRR_FIX4K_E0000");
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soc_display_4k_mtrr(MTRR_FIX_4K_E8000, 0xe8000,
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"IA32_MTRR_FIX4K_E8000");
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soc_display_4k_mtrr(MTRR_FIX_4K_F0000, 0xf0000,
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"IA32_MTRR_FIX4K_F0000");
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soc_display_4k_mtrr(MTRR_FIX_4K_F8000, 0xf8000,
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"IA32_MTRR_FIX4K_F8000");
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address_bits = cpu_phys_address_size();
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address_mask = (1ULL << address_bits) - 1;
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/* Display the fixed MTRRs */
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display_mtrrcap();
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display_mtrr_def_type();
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display_64k_mtrr();
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display_16k_mtrr(MTRR_FIX_16K_80000, 0x80000, "IA32_MTRR_FIX16K_80000");
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display_16k_mtrr(MTRR_FIX_16K_A0000, 0xa0000, "IA32_MTRR_FIX16K_A0000");
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display_4k_mtrr(MTRR_FIX_4K_C0000, 0xc0000, "IA32_MTRR_FIX4K_C0000");
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display_4k_mtrr(MTRR_FIX_4K_C8000, 0xc8000, "IA32_MTRR_FIX4K_C8000");
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display_4k_mtrr(MTRR_FIX_4K_D0000, 0xd0000, "IA32_MTRR_FIX4K_D0000");
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display_4k_mtrr(MTRR_FIX_4K_D8000, 0xd8000, "IA32_MTRR_FIX4K_D8000");
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display_4k_mtrr(MTRR_FIX_4K_E0000, 0xe0000, "IA32_MTRR_FIX4K_E0000");
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display_4k_mtrr(MTRR_FIX_4K_E8000, 0xe8000, "IA32_MTRR_FIX4K_E8000");
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display_4k_mtrr(MTRR_FIX_4K_F0000, 0xf0000, "IA32_MTRR_FIX4K_F0000");
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display_4k_mtrr(MTRR_FIX_4K_F8000, 0xf8000, "IA32_MTRR_FIX4K_F8000");
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address_bits = cpu_phys_address_size();
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address_mask = (1ULL << address_bits) - 1;
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/* Display the variable MTRRs */
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for (i = 0; i < variable_mtrrs; i++)
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soc_display_variable_mtrr(MTRR_PHYS_BASE(i), i,
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address_mask);
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}
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/* Display the variable MTRRs */
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variable_mtrrs = get_var_mtrr_count();
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for (i = 0; i < variable_mtrrs; i++)
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display_variable_mtrr(i, address_mask);
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}
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asmlinkage void display_mtrrs(void)
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{
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if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
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_display_mtrrs();
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}
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@ -20,13 +20,11 @@
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*/
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int get_free_var_mtrr(void)
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{
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msr_t msr, maskm;
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msr_t maskm;
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int vcnt;
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int i;
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/* Read MTRRCap and get vcnt - variable memory type ranges. */
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msr = rdmsr(MTRR_CAP_MSR);
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vcnt = msr.lo & 0xff;
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vcnt = get_var_mtrr_count();
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/* Identify the first var mtrr which is not valid. */
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for (i = 0; i < vcnt; i++) {
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@ -66,7 +66,7 @@
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1:
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#endif
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/* Display the MTRRs */
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call soc_display_mtrrs
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call display_mtrrs
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/*
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* The stack contents are initialized in src/soc/intel/common/stack.c
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@ -15,10 +15,10 @@
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#include <arch/early_variables.h>
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#include <console/console.h>
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#include <cpu/x86/mtrr.h>
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#include <fsp/car.h>
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#include <fsp/util.h>
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#include <program_loading.h>
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#include <soc/intel/common/util.h>
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#include <timestamp.h>
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FSP_INFO_HEADER *fih_car CAR_GLOBAL;
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@ -95,7 +95,7 @@ asmlinkage void after_cache_as_ram(void *chipset_context)
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{
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timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END);
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printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n");
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soc_display_mtrrs();
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display_mtrrs();
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after_cache_as_ram_stage();
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}
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@ -18,7 +18,6 @@
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#define _INTEL_COMMON_RAMSTAGE_H_
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#include <fsp/util.h>
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#include <soc/intel/common/util.h>
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#include <stdint.h>
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/*
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@ -22,7 +22,6 @@
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#include <memory_info.h>
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#include <fsp/car.h>
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#include <fsp/util.h>
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#include <soc/intel/common/util.h>
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#include <soc/intel/common/mma.h>
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#include <soc/pei_wrapper.h>
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#include <soc/pm.h> /* chip_power_state */
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|
|||
|
|
@ -38,12 +38,12 @@ void *setup_stack_and_mtrrs(void)
|
|||
uint32_t *slot;
|
||||
|
||||
/* Display the MTRRs */
|
||||
soc_display_mtrrs();
|
||||
display_mtrrs();
|
||||
|
||||
/* Top of stack needs to be aligned to a 8-byte boundary. */
|
||||
slot = (void *)romstage_ram_stack_top();
|
||||
num_mtrrs = 0;
|
||||
max_mtrrs = soc_get_variable_mtrr_count(NULL);
|
||||
max_mtrrs = get_var_mtrr_count();
|
||||
|
||||
/*
|
||||
* The upper bits of the MTRR mask need to set according to the number
|
||||
|
|
|
|||
|
|
@ -11,8 +11,8 @@
|
|||
|
||||
#include <console/console.h>
|
||||
#include <console/streams.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <fsp/util.h>
|
||||
#include <soc/intel/common/util.h>
|
||||
|
||||
asmlinkage size_t fsp_write_line(uint8_t *buffer, size_t number_of_bytes)
|
||||
{
|
||||
|
|
@ -28,9 +28,7 @@ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init,
|
|||
const FSPM_UPD *fspm_old_upd,
|
||||
const FSPM_UPD *fspm_new_upd)
|
||||
{
|
||||
/* Display the MTRRs */
|
||||
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
|
||||
soc_display_mtrrs();
|
||||
display_mtrrs();
|
||||
|
||||
/* Display the UPD values */
|
||||
if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
|
||||
|
|
@ -62,9 +60,7 @@ void fsp_debug_after_memory_init(uint32_t status)
|
|||
if (IS_ENABLED(CONFIG_VERIFY_HOBS))
|
||||
fsp_verify_memory_init_hobs();
|
||||
|
||||
/* Display the MTRRs */
|
||||
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
|
||||
soc_display_mtrrs();
|
||||
display_mtrrs();
|
||||
}
|
||||
|
||||
/*-----------
|
||||
|
|
@ -75,9 +71,7 @@ void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init,
|
|||
const FSPS_UPD *fsps_old_upd,
|
||||
const FSPS_UPD *fsps_new_upd)
|
||||
{
|
||||
/* Display the MTRRs */
|
||||
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
|
||||
soc_display_mtrrs();
|
||||
display_mtrrs();
|
||||
|
||||
/* Display the UPD values */
|
||||
if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
|
||||
|
|
@ -99,9 +93,7 @@ void fsp_debug_after_silicon_init(uint32_t status)
|
|||
if (IS_ENABLED(CONFIG_DISPLAY_HOBS))
|
||||
fsp_display_hobs();
|
||||
|
||||
/* Display the MTRRs */
|
||||
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
|
||||
soc_display_mtrrs();
|
||||
display_mtrrs();
|
||||
}
|
||||
|
||||
/*-----------
|
||||
|
|
@ -129,7 +121,5 @@ void fsp_debug_after_notify(uint32_t status)
|
|||
if (IS_ENABLED(CONFIG_DISPLAY_HOBS))
|
||||
fsp_display_hobs();
|
||||
|
||||
/* Display the MTRRs */
|
||||
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
|
||||
soc_display_mtrrs();
|
||||
display_mtrrs();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -12,8 +12,8 @@
|
|||
|
||||
#include <bootstate.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <fsp/util.h>
|
||||
#include <soc/intel/common/util.h>
|
||||
#include <string.h>
|
||||
#include <timestamp.h>
|
||||
|
||||
|
|
@ -70,9 +70,7 @@ static void fsp_notify_dummy(void *arg)
|
|||
{
|
||||
enum fsp_notify_phase phase = (uint32_t)arg;
|
||||
|
||||
/* Display the MTRRs */
|
||||
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
|
||||
soc_display_mtrrs();
|
||||
display_mtrrs();
|
||||
|
||||
fsp_notify(phase);
|
||||
if (phase == READY_TO_BOOT)
|
||||
|
|
|
|||
|
|
@ -99,10 +99,17 @@ void x86_mtrr_check(void);
|
|||
* This function needs to be called after the first MTRR solution is derived. */
|
||||
void mtrr_use_temp_range(uintptr_t begin, size_t size, int type);
|
||||
|
||||
static inline int get_var_mtrr_count(void)
|
||||
{
|
||||
return rdmsr(MTRR_CAP_MSR).lo & MTRR_CAP_VCNT;
|
||||
}
|
||||
|
||||
void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
|
||||
unsigned int type);
|
||||
int get_free_var_mtrr(void);
|
||||
|
||||
asmlinkage void display_mtrrs(void);
|
||||
|
||||
/*
|
||||
* Set the MTRRs using the data on the stack from setup_stack_and_mtrrs.
|
||||
* Return a new top_of_stack value which removes the setup_stack_and_mtrrs data.
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
config SOC_INTEL_COMMON
|
||||
bool
|
||||
select HAVE_DISPLAY_MTRRS
|
||||
help
|
||||
common code for Intel SOCs
|
||||
|
||||
|
|
@ -14,10 +15,6 @@ source "src/soc/intel/common/pch/Kconfig"
|
|||
comment "Intel SoC Common coreboot stages"
|
||||
source "src/soc/intel/common/basecode/Kconfig"
|
||||
|
||||
config DISPLAY_MTRRS
|
||||
bool "MTRRs: Display the MTRR settings"
|
||||
default n
|
||||
|
||||
config DISPLAY_SMM_MEMORY_MAP
|
||||
bool "SMM: Display the SMM memory map"
|
||||
default n
|
||||
|
|
|
|||
|
|
@ -4,23 +4,18 @@ subdirs-y += basecode/
|
|||
subdirs-y += block/
|
||||
subdirs-y += pch/
|
||||
|
||||
bootblock-y += util.c
|
||||
|
||||
verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
|
||||
|
||||
bootblock-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
|
||||
|
||||
romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
|
||||
romstage-y += util.c
|
||||
romstage-$(CONFIG_MMA) += mma.c
|
||||
romstage-y += smbios.c
|
||||
|
||||
postcar-y += util.c
|
||||
postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
|
||||
|
||||
ramstage-y += hda_verb.c
|
||||
ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
|
||||
ramstage-y += util.c
|
||||
ramstage-$(CONFIG_MMA) += mma.c
|
||||
ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c
|
||||
ramstage-y += vbt.c
|
||||
|
|
|
|||
|
|
@ -1,26 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _INTEL_COMMON_UTIL_H_
|
||||
#define _INTEL_COMMON_UTIL_H_
|
||||
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <stdint.h>
|
||||
|
||||
asmlinkage void soc_display_mtrrs(void);
|
||||
uint32_t soc_get_variable_mtrr_count(uint64_t *msr);
|
||||
|
||||
#endif /* _INTEL_COMMON_UTIL_H_ */
|
||||
|
|
@ -16,6 +16,7 @@
|
|||
ifeq ($(CONFIG_SOC_INTEL_QUARK),y)
|
||||
|
||||
subdirs-y += romstage
|
||||
subdirs-y += ../../../cpu/x86/mtrr
|
||||
subdirs-y += ../../../cpu/x86/tsc
|
||||
|
||||
bootblock-y += bootblock/esram_init.S
|
||||
|
|
|
|||
|
|
@ -15,10 +15,10 @@
|
|||
*/
|
||||
#include <bootblock_common.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <program_loading.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/intel/common/util.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/reg_access.h>
|
||||
|
||||
|
|
@ -112,8 +112,7 @@ void bootblock_soc_init(void)
|
|||
if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_INIT_ENTRY))
|
||||
light_sd_led();
|
||||
|
||||
/* Display the MTRRs */
|
||||
soc_display_mtrrs();
|
||||
display_mtrrs();
|
||||
}
|
||||
|
||||
void platform_prog_run(struct prog *prog)
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
#ifndef _SOC_RAMSTAGE_H_
|
||||
#define _SOC_RAMSTAGE_H_
|
||||
|
||||
#include <arch/cpu.h>
|
||||
#include <chip.h>
|
||||
#include <device/device.h>
|
||||
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@
|
|||
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <soc/intel/common/util.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/reg_access.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -40,8 +40,6 @@ smm_region
|
|||
smm_region_size
|
||||
soc_after_ram_init
|
||||
soc_display_memory_init_params
|
||||
soc_display_mtrrs
|
||||
soc_get_variable_mtrr_count
|
||||
soc_memory_init_params
|
||||
soc_pre_ram_init
|
||||
southbridge_smi_handler
|
||||
|
|
|
|||
|
|
@ -23,8 +23,6 @@ platform_segment_loaded
|
|||
save_chromeos_gpios
|
||||
soc_after_ram_init
|
||||
soc_display_memory_init_params
|
||||
soc_display_mtrrs
|
||||
soc_get_variable_mtrr_count
|
||||
soc_memory_init_params
|
||||
soc_pre_ram_init
|
||||
southbridge_smi_handler
|
||||
|
|
|
|||
|
|
@ -22,8 +22,6 @@ map_oprom_vendev
|
|||
platform_prog_run
|
||||
platform_segment_loaded
|
||||
save_chromeos_gpios
|
||||
soc_display_mtrrs
|
||||
soc_get_variable_mtrr_count
|
||||
stage_cache_add
|
||||
stage_cache_load_stage
|
||||
timestamp_get
|
||||
|
|
|
|||
|
|
@ -9,8 +9,6 @@ mainboard_check_ec_image
|
|||
mainboard_post
|
||||
platform_prog_run
|
||||
platform_segment_loaded
|
||||
soc_display_mtrrs
|
||||
soc_get_variable_mtrr_count
|
||||
stage_cache_add
|
||||
stage_cache_load_stage
|
||||
timestamp_get
|
||||
|
|
|
|||
Loading…
Reference in New Issue