soc/intel/apollolake: configure interrupt trigger mode
Provide trigger option to configure APIC, sci, smi, nmi interrupts. Change-Id: I1b553fb4ed1b43aba62346f5b758f8d082606510 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/14353 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -53,28 +53,28 @@
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PAD_PULL(pull))
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/* General purpose input, routed to APIC */
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#define PAD_CFG_GPI_APIC(pad, pull, rst) \
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#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
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PAD_IRQ_CFG(IOAPIC, LEVEL, NONE), PAD_PULL(pull))
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PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull))
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/* General purpose input, routed to SMI */
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#define PAD_CFG_GPI_SMI(pad, pull, rst, inv) \
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#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
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PAD_IRQ_CFG(SMI, LEVEL, inv), PAD_PULL(pull))
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PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull))
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/* General purpose input, routed to SCI */
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#define PAD_CFG_GPI_SCI(pad, pull, rst, inv) \
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#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
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PAD_IRQ_CFG(SCI, LEVEL, inv), PAD_PULL(pull))
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PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull))
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/* General purpose input, routed to NMI */
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#define PAD_CFG_GPI_NMI(pad, pull, rst, inv) \
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#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
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PAD_IRQ_CFG(NMI, LEVEL, inv), PAD_PULL(pull))
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PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull))
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struct pad_config {
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uint32_t config0;
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