intel/cyan: Fix crossystem "wpsw_cur" status

The GPIO mapping was incorrect for wpsw_cur.
The GPIOs for East community were in two ranges:
 0: INT33FF:02 GPIOS [373 - 384] PINS [0 - 11] and
12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26]

The discontinuity was not accounted for, hence the error.
The original offset was 0x16 whereas it should be 0x13

BUG=chrome-os-partner:42798
BRANCH=None
TEST=Run crossystem and test wpsw_cur entry. If screw is present,
it should be 1 and if not present, it should be 0

Change-Id: I2faea1fe1415c9d4cb23444d03c7c9d47c87e8e5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 30ac96f606a5618e9ef12bac3f50fac433141acd
Original-Change-Id: I166a7c3e15a990b507ae3c13e15ab56bee7fb917
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286534
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/11010
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/mainboard/google/cyan/acpi/chromeos.asl

@@ -33,5 +33,5 @@
 Name(OIPG, Package() {
 	/* No physical recovery button */
 	Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" },
-	Package () { 0x0003, 1, 0x10016, "Braswell" },
+	Package () { 0x0003, 1, 0x10013, "Braswell" },
 })