amd/stoneyridge: Add GNB IOAPIC init
Use standard coreboot function to set virtual wire mode on the GNB IOAPIC. BUG=b:74104946 TEST=Check GNB IOAPIC debug output on serial. Change-Id: I4ff8698419890df1459b1107f0861cf8277a99b0 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -15,6 +15,7 @@
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#include <arch/io.h>
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#include <arch/ioapic.h>
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include <cbmem.h>
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@ -69,12 +70,20 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index,
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static void read_resources(device_t dev)
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{
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struct resource *res;
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/*
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* This MMCONF resource must be reserved in the PCI domain.
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* It is not honored by the coreboot resource allocator if it is in
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* the CPU_CLUSTER.
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*/
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mmconf_resource(dev, MMIO_CONF_BASE);
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/* NB IOAPIC2 resource */
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res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */
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res->base = IO_APIC2_ADDR;
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res->size = 0x00001000;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
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@ -165,6 +174,7 @@ static void set_resources(device_t dev)
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static void northbridge_init(struct device *dev)
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{
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setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1);
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}
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static unsigned long acpi_fill_hest(acpi_hest_t *hest)
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