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mb/clevo/l140cu: drop System76 EC 

Drop System76 EC, since the ODM board does not use it. Clevo EC FW
support will be added and hooked up cleanly in the follow-up changes.

Change-Id: I06abbde238be6d25842472a6a82159413ab52ef5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59816
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner 2021-11-22 21:13:49 +01:00
parent e1e65cb0f1
commit d6ac7a9a3a
6 changed files with 0 additions and 45 deletions
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1
src/mainboard/clevo/cml-u/Kconfig
View File

@ -20,7 +20,6 @@ config BOARD_CLEVO_CMLU_COMMON
config BOARD_CLEVO_L140CU_BASE
bool
select BOARD_CLEVO_CMLU_COMMON
select EC_SYSTEM76_EC
select HAVE_SPD_IN_CBFS
if BOARD_CLEVO_CMLU_COMMON

11
src/mainboard/clevo/cml-u/acpi/gpe.asl
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@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
// GPP_D9 SCI
Method (_L29, 0, Serialized) {
Debug = Concatenate("GPE _L29: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
If (\_SB.PCI0.LPCB.EC0.ECOK) {
If (\_SB.PCI0.LPCB.EC0.WFNO == One) {
Notify(\_SB.LID0, 0x80)
}
}
}

13
src/mainboard/clevo/cml-u/acpi/mainboard.asl
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@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#define EC_GPE_SCI 0x50 /* GPP_E16 */
#define EC_GPE_SWI 0x29 /* GPP_D9 */
#include <ec/system76/ec/acpi/ec.asl>
Scope (\_SB) {
#include "sleep.asl"
}
Scope (\_GPE) {
#include "gpe.asl"
}

11
src/mainboard/clevo/cml-u/acpi/sleep.asl
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@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Method called from _PTS prior to enter sleep state */
Method (MPTS, 1) {
\_SB.PCI0.LPCB.EC0.PTS (Arg0)
}
/* Method called from _WAK prior to wakeup */
Method (MWAK, 1) {
\_SB.PCI0.LPCB.EC0.WAK (Arg0)
}

2
src/mainboard/clevo/cml-u/dsdt.asl
View File

@ -28,6 +28,4 @@ DefinitionBlock(
{
#include <drivers/pc80/pc/ps2_controller.asl>
}
#include "acpi/mainboard.asl"
}

7
src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
View File

@ -183,13 +183,6 @@ chip soc/intel/cannonlake
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on # LPC Interface
# LPC configuration from lspci -s 1f.0 -xxx
# Address 0x88: Decode 0x68 - 0x6F (EC PM channel)
register "gen1_dec" = "0x00040069"
# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
register "gen2_dec" = "0x00fc0e01"
# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
register "gen3_dec" = "0x00fc0f01"
chip drivers/pc80/tpm # TPM
device pnp 0c31.0 on end
end