GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/alderlake: Add support for more CPU PCIe RP UPDs 

There are 3 more CPU PCIe RP UPDs that are the current code is not setting,
and some boards may want to set these, so this patch adds support to set
these UPDs. The default values for any existing boards using these UPDs
should not change with this patch.

The UPDs are:
 - CpuPcieRpDetectTimeoutMs
 - CpuPcieRpAspm
 - CpuPcieRpSlotImplemented

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Id48019f984e8e53ff3ce0c3c23e02dab65112c99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66197
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak 2022-07-27 09:53:58 -06:00 committed by Paul Fagerburg
parent 05f0e3fe86
commit d6b763ca63
1 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/intel/alderlake/fsp_params.c
View File

@ -895,7 +895,13 @@ static void fill_fsps_cpu_pcie_params(FSP_S_CONFIG *s_cfg,
s_cfg->CpuPcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER);
s_cfg->CpuPcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG)
|| CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
s_cfg->CpuPcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
s_cfg->PtmEnabled[i] = 0;
if (rp_cfg->pcie_rp_aspm)
s_cfg->CpuPcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm);
if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN))
s_cfg->CpuPcieRpSlotImplemented[i] = 0;
}
s_cfg->CpuPcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
}