soc/intel/apollolake: remove duplicate gpio GPE defines
Remove the duplicate MISCCFG_GPE0_DW* macros that are already present in the common gpio code. Change-Id: Iad75e5f7e276b37b5861f0c9a3bb0bb2824a638c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -276,13 +276,6 @@
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#define GPIO_MAX_NUM_PER_GROUP 32
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#define MISCCFG_GPE0_DW0_SHIFT 8
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#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT)
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#define MISCCFG_GPE0_DW1_SHIFT 12
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#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
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#define MISCCFG_GPE0_DW2_SHIFT 16
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#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)
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/* Host Software Pad Ownership Register.
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* The pins in the community are divided into 3 groups :
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* GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95
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