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soc/intel/apollolake: remove duplicate gpio GPE defines 

Remove the duplicate MISCCFG_GPE0_DW* macros that are already present
in the common gpio code.

Change-Id: Iad75e5f7e276b37b5861f0c9a3bb0bb2824a638c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Aaron Durbin 2017-08-17 17:04:08 -06:00
parent f771de445d
commit d6bd825d6c
1 changed files with 0 additions and 7 deletions
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7
src/soc/intel/apollolake/include/soc/gpio_glk.h
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@ -276,13 +276,6 @@
#define GPIO_MAX_NUM_PER_GROUP 32 #define GPIO_MAX_NUM_PER_GROUP 32
#define MISCCFG_GPE0_DW0_SHIFT 8
#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT)
#define MISCCFG_GPE0_DW1_SHIFT 12
#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
#define MISCCFG_GPE0_DW2_SHIFT 16
#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)
/* Host Software Pad Ownership Register. /* Host Software Pad Ownership Register.
* The pins in the community are divided into 3 groups : * The pins in the community are divided into 3 groups :
* GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95 * GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95