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sb/intel/bd82x6x: fix linking for non-native raminit case 

Commit 45d4b17 [nb/intel/sandybridge: Move southbridge code to bd82x6x]
moved early_pch_init() to the southbridge, but failed to include
early_pch.c for the non-native raminit case, which now fails to link.
As all boards default to native raminit, this was missed by the autobuilder.

Adjust early_pch.c to be compiled regardles of ram init type used

Test: build/boot google/stout with MRC ram init selected

Change-Id: I50db30fda9a1099fb434c04ea97bcc38f8455233
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Matt DeVillier 2019-04-21 16:49:14 -05:00 committed by Patrick Georgi
parent 420d7e009d
commit d6d6771b97
1 changed files with 2 additions and 1 deletions
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3
src/southbridge/intel/bd82x6x/Makefile.inc
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@ -40,9 +40,10 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c pch.c
romstage-y += early_smbus.c me_status.c romstage-y += early_smbus.c me_status.c
romstage-y += early_spi.c romstage-y += early_spi.c
romstage-y += early_rcba.c romstage-y += early_rcba.c
romstage-y += early_pch.c
ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
romstage-y += early_thermal.c early_pch.c early_me.c early_usb.c romstage-y += early_thermal.c early_me.c early_usb.c
else else
romstage-y += early_me_mrc.c early_usb_mrc.c romstage-y += early_me_mrc.c early_usb_mrc.c
endif endif